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kgalburt
Visitor
Visitor
2,075 Views
Registered: ‎05-24-2017

SystemVerilog in System Generator

Hi,

 

Our goal is to take synthesized SystemVerilog code from design team and implement it in System Generator for complete mixed signal system simulation in Simulink and subsequent emulation on FPGA. My research shows that at present SystemVerilog is not supported in System Generator and I see no obvious work around.

 

Is there a way to get System Verilog code into System Generator?

 

For Xilinx team, Is there a plan to implement SystemVerilog support in System Generator? If yes, what is the timeline?

 

Thanks

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balkris
Xilinx Employee
Xilinx Employee
1,821 Views
Registered: ‎08-01-2008

Currently System Verilog feature is not supported by Sysgen . I have created request so it may added in future release

CR-978908 created
Thanks for reporting this issue
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
1,775 Views
Registered: ‎08-01-2008

@kgalburt , I would like to know if you have any further questions on this issue. There is no plan for System Verilog support in sysgen
Thanks and Regards
Balkrishan
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