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Adventurer
Adventurer
3,035 Views
Registered: ‎11-11-2015

The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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Hi everyone,

 

I'm using DDS compiler 6.0 1 in System Generator 2015.4. The Virtex 7 FPGA clock frequency is 250MHz and I want to generate a 10MHz sine wave.

ProgrammableDDS.png

In the configuration of DDS compiler, I selected hardware parameters and the phase width is 30.

 

So I calculated that the phase angle increment values as follows.

 

 

PhaseIncrementValue = (10e6 * 2^30)/250e6 = 42949672.96

 

Since the config_tdata_pinc port of DDS Compiler expects unsigned fix_point 30_30 input. I calculated the value of pinc as

 

pinc = PhaseIncrementValue/2^30 = 0.04

 

 

However, it seems that this configuration is incorrect, since the DDS output is a constant value 1.

 

Here I attached my block design in System Generator. Can anyone help me check it?

 

Thank you very much.

 

Regards,

Tong

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Adventurer
Adventurer
4,676 Views
Registered: ‎11-11-2015

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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Hi @austin

 

Thank you very much.

 

I found out the problem. Sorry I made a very stupid mistake. I connected the Gateway Out with data_tvalid instead of data_tready.

The value of the constant should be 0.04, since the config_tdata_pinc port requires Fixed_30_30 input.

 

ProgrammableDDS4.png

 

The result is good after the modification.

 

In my understanding, the clock source is from a FPGA pin which has been linked with a clock chip on FPGA board. But we don't need to specify the pin location while implementing DSP algorithms in System Generator. The clock capable pins won't show up until the Xilinx IP has been generated from System Generator design.

 

Thanks.

 

Regards,

Tong

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8 Replies
Scholar austin
Scholar
3,033 Views
Registered: ‎02-27-2008

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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42949672.96 is the constant,

 

(42,949,673 as the integer used to set the frequency)

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
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Registered: ‎11-11-2015

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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@austin

 

Hi Austin, 

 

Thank you very much. I modified my design and set the constant to 42,949,673, but the result still remains the same. I don't know where went wrong.

ProgrammableDDS2.png

 

I also tried to use the "Constant" block from Xilinx, but the result is still incorrect.

 

ProgrammableDDS3.png

 

 

Is there any other possible mistake?

 

Regards,

Tong

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Scholar austin
Scholar
2,965 Views
Registered: ‎02-27-2008

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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Where is the clock?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
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Registered: ‎11-11-2015

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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@austin

 

Thank you.

I configured the clock in "System Generator" block. The clock frequency is 250MHz.

DDSclock.png

 

Regards,

Tong

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Scholar austin
Scholar
2,947 Views
Registered: ‎02-27-2008

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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Where is the source of this clock?  I do not see it coming in through an IBUFG on a clock capable pin and being named....

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
4,677 Views
Registered: ‎11-11-2015

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

Jump to solution

Hi @austin

 

Thank you very much.

 

I found out the problem. Sorry I made a very stupid mistake. I connected the Gateway Out with data_tvalid instead of data_tready.

The value of the constant should be 0.04, since the config_tdata_pinc port requires Fixed_30_30 input.

 

ProgrammableDDS4.png

 

The result is good after the modification.

 

In my understanding, the clock source is from a FPGA pin which has been linked with a clock chip on FPGA board. But we don't need to specify the pin location while implementing DSP algorithms in System Generator. The clock capable pins won't show up until the Xilinx IP has been generated from System Generator design.

 

Thanks.

 

Regards,

Tong

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Scholar austin
Scholar
2,930 Views
Registered: ‎02-27-2008

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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Great!

 

I am glad you found it.  I was just suggesting things that might have been incorrectly done.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
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Registered: ‎11-11-2015

Re: The config_tdata_pinc port of DDS Compiler 6.0 1 in Programmable mode

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Hi @austin

 

Thank you very much.

I'm so glad that the problem has been solved.

 

Regards,

Tong

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