UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer wangxiaoliang
Observer
11,335 Views
Registered: ‎09-12-2008

The problem of FFT IP core

Jump to solution
 
0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
11,963 Views
Registered: ‎08-14-2007

Re: The problem of FFT IP core

Jump to solution
It's basically a simulation problem. You didn't compile myfft in the do file. Add "vlog myfft.v" before running vsim command will sovle the problem 

View solution in original post

0 Kudos
9 Replies
Observer wangxiaoliang
Observer
11,312 Views
Registered: ‎09-12-2008

Re: The problem of FFT IP core

Jump to solution

Hi:

I'm sorry.There is no content in my question.What is that I creat two projects,in which I do the same thing.But now fft4 can work ,while the other cannot.

Where are the problems? The transcripts are in it.

Wish for your help!

0 Kudos
Observer wangxiaoliang
Observer
11,308 Views
Registered: ‎09-12-2008

Re: The problem of FFT IP core

Jump to solution

Hi:

The error messege is this:

 

# Top level modules:
#  fft_top
# Model Technology ModelSim SE vlog 6.3c Compiler 2007.09 Sep 11 2007
# -- Compiling module glbl
#
# Top level modules:
#  glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -lib work -t 1ps fft_top glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: fft_top.v(61): Module 'myfft' is not defined.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./fft_top.fdo PAUSED at line 7

 

 

PLZ HELP

0 Kudos
Explorer
Explorer
11,964 Views
Registered: ‎08-14-2007

Re: The problem of FFT IP core

Jump to solution
It's basically a simulation problem. You didn't compile myfft in the do file. Add "vlog myfft.v" before running vsim command will sovle the problem 

View solution in original post

0 Kudos
Observer wangxiaoliang
Observer
11,286 Views
Registered: ‎09-12-2008

Re: The problem of FFT IP core

Jump to solution
Thank you! The problem is solved. But why the problem is in verilog, not in vhdl?
0 Kudos
11,188 Views
Registered: ‎11-05-2008

Re: The problem of FFT IP core

Jump to solution

excuse me, can anybody tell me why I get zero results from fft when I simulate using ISE simulator. I don't know about verilog very much but I think I did the same in VHDL, however when I tried to simulate your file I got zero results.

 

please help me ASAP, I am in a bad need to know how this core works please.

0 Kudos
Highlighted
Observer wangxiaoliang
Observer
11,179 Views
Registered: ‎09-12-2008

Re: The problem of FFT IP core

Jump to solution

Hello:

If you have output,that means the core works in a right way,maybe you should check your testbench,and the timing.

0 Kudos
Visitor imranqureshi
Visitor
10,510 Views
Registered: ‎01-21-2009

Re: The problem of FFT IP core

Jump to solution

Hi,

plz set 500ns time then check!

 

0 Kudos
Visitor imranqureshi
Visitor
10,507 Views
Registered: ‎01-21-2009

Re: The problem of FFT IP core

Jump to solution
set 500us simulation time
0 Kudos
Visitor deba_techno
Visitor
5,957 Views
Registered: ‎10-26-2011

Re: The problem of FFT IP core

Jump to solution

@imranqureshi wrote:
set 500us simulation time

i have tested the rar fft4 code, with 500us just for experimenting. got "0" result. can u sir, plz fix the problem.

0 Kudos