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pidioboris
Visitor
Visitor
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Registered: ‎10-08-2007

Timing constraint error on FPGA Virtex II Pro xc2vp50

Hello everybody,
 
I'm trying to implement a fixed-point 128-tap (tunable) LowPass FIR Filter on the FPGA Virtex II Pro xc2vp50.
I've used the FDATool and the Filter Design HDL Coder from Mathworks to design the filter and to generate its VHDL code.
There are some default logic functions that may be modified or replaced within the FPGA however the supplied .ucf file shouldn' t be modified.
The implementation is done using Xilinx ISE Foundation 9.2.04i. I'm getting an error information about timing constraint. I've tried a lot of options in Synthesizing and Place and Route tools but nothing changes, and now I just don't have any idea of what I could try.
Here the error message I'm getting:
 

Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint.  A physical timing constraint summary will appear in the map report.  This summary will show a MINIMUM net delay for the paths.  For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual.  For more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter.

 

I also include a part of my diagram.

 

I hope somebody will have some idea on how to solve this problem.



Message Edited by pidioboris on 03-14-2008 06:47 AM
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3 Replies
jbass
Xilinx Employee
Xilinx Employee
11,322 Views
Registered: ‎08-02-2007

You are getting this error message because a constraint is unable to be met because one or more paths covered by that constraint have component delays greater than the timespec allows.  This means that no matter where the components in those paths are placed and routed, it will be impossible to attain timing closure.

You can either relax the timing constraint, add a pipeline stage to shorten your combinatorial path, or redesign to use fewer logic levels in the path to decrease the number of components.
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pidioboris
Visitor
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Registered: ‎10-08-2007

Thanks jbass for your comments!
 
I have added pipelines in my design and lowered the number of taps in the filter (I guess that decreases the number of components). However I'm having the same failure in Timing constraints. I've tried the highest effort in PAR and it decreased the delay a little but it takes a lot of time to run and also it doesn' t solve the problem. Furthermore, I shouldn' t change the UCF file that has been provided (in order to relax the constraint). Is there something else that I could try? I'm really struggling with this one. Thanks for your help.


Message Edited by pidioboris on 03-18-2008 07:14 AM
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qxl052000
Newbie
Newbie
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Registered: ‎04-17-2008

HI, man
 
I have the exactly same problem with you.
 
You can try to slow down your clock -- not using the full speed clock, but half of it. It works.
 
But I can not use this solution, because I need the full speed. How can I do?
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