03-14-2008 06:45 AM - edited 03-14-2008 06:47 AM
Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary will appear in the map report. This summary will show a MINIMUM net delay for the paths. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual. For more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter.
I also include a part of my diagram.
I hope somebody will have some idea on how to solve this problem.
03-14-2008 09:31 AM
03-18-2008 07:00 AM - edited 03-18-2008 07:14 AM
04-17-2008 02:48 PM