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3,063 Views
Registered: ‎05-23-2012

Timing issue with Sysgen but no timing issue in ISE

I've imported a VHDL design to the Sysgen model and encountered the timing issue. However when I ran in the ISE with the same timing constraint, I didn't get the timing issue.

 

Does anyone know why I have this problem? How to modify the design according to the timing report?

 

Thanks in advance.

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2 Replies
Scholar austin
Scholar
3,056 Views
Registered: ‎02-27-2008

Re: Timing issue with Sysgen but no timing issue in ISE

m,

 

Everytime you place and route, different paths may be used, and timing violations may appear.

 

Timing closure  involves examining the failing path, an then re-architecting, rewriting rtl, use of placement constraints, etc. to resolve.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/ug612.pdf

 

http://www.xilinx.com/training/fpga/timing-closure-video.htm

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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3,049 Views
Registered: ‎05-23-2012

Re: Timing issue with Sysgen but no timing issue in ISE

Thank you for your reply.

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