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Anonymous
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Two’s Complement Multiplier with DSP48E1

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Hello Everyone,

I would to know more about output on multiplier in DSP48E1.

I saw in another documentation about Two’s Complement Multiplier, when we multiply two arrays with N bits on output will have one array with width 2N and have two signed bits.

I need implement several DSP in Cascate, like it "7 Series DSP48E1 Slice" (UG479) pág. 49.

I believe that for every multiplication done I'll have a bit more than you can change the value end of my filter.

I would to know if output the multipler need these handling or this already handled by the partial products.

I maked test with DSP48E1 primitive and did not recognize the two-bit signal.

I studied "7 Series DSP48E1 Slice" (UG479), but I didn't find this information.

Sorry guys if there is already any post with this information, I lookup all forum but could not find any post that can solve my question.

It is my first post. I hope first of many.

Any help is welcome.

Thank you for your attention.

Best Regards,

Raphael Augusto José

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Scholar
Scholar
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Registered: ‎02-27-2008

r,

 

A signd multiplier takes two signed numbers, and provides you with the signed product (answer).

 

Thwe DSP48 uses 2's complement signed number format.  The result is a 2's complement result.

 

Page 49 refers to an adder cascade.  The adders are also 2's complement capable.

 

In general, the only thing you need to decide, is how to throw away the lower part of the products, or how to form a longer sum (beyond 28 bits).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
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Registered: ‎02-27-2008

r,

 

A signd multiplier takes two signed numbers, and provides you with the signed product (answer).

 

Thwe DSP48 uses 2's complement signed number format.  The result is a 2's complement result.

 

Page 49 refers to an adder cascade.  The adders are also 2's complement capable.

 

In general, the only thing you need to decide, is how to throw away the lower part of the products, or how to form a longer sum (beyond 28 bits).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Anonymous
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Hello Austin,

Sorry for my delay in my reply.

Your answer was helpful.

Thank you.
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