11-27-2011 02:25 AM
Hello,one interesting question i came across by one of my friends Luis Manuel that , how can we see the clock of system generator?
I have written one verilog code, in which:
Initialization of d as d=0, then doing d=~d at every positive edge of clk.
clk_out=clk has been assigned.
module firs(clk,ce,clk_out,d); input clk,ce; output clk_out; output reg d; assign clk_out=clk; initial begin d=0; end always @(posedge clk) begin d=~d; end endmodule
After running the program, in Wavescope i get is,
Clk_out is always remaining 0.
So always@(posedge clk) whatever operation was there =>Invert d that took place, but we are not able to see the clk.
11-27-2011 03:17 AM
11-27-2011 11:48 AM
you are trying to see two signals from the Simulink domain (after gateway out) in Wavescope that is used to plot signals from System Generator, are you sure this is allowed?
11-27-2011 09:19 PM
I'm not 100% sure I understand your problem because it involves System Generator, but I imagine it is because you're trying to sample clk_out using clk as the sampling clock. If you sample a signal using that signal as a trigger, the value will be constant and either zero or one depending on the clock edge you're sampling on (disregarding setup/hold times, etc.)
As an analogy, imagine trying to take a photograph of a camera in a mirror. From viewing a series of photos, you might think that the camera's shutter is always open, but this is just because of your sampling method. You'd need to sample the clock signal at both edges of the clock (or somehow take a photograph of the camera when the shutter is closed), or use a different, faster clock.
11-27-2011 09:37 PM