06-09-2014 09:16 PM
I am trying to interface a DAC board with a ml605 fgpa. My system basically takes input ( sine or QAM signals ) from Simulink, passes through a block which has few complex multiplication, addition, and then needs to be sent out via the DAC.
But, when I do it on system generator, I am not able to send the data out of the fpga to the DAC via non memory mapped ports!
Is there a way in which I can just load the data to fpga and instead of using co simulation, I could just send the data out to the DAC board normally.
Also any help with respect to using co simulation itself to do this work will be great!
06-09-2014 10:56 PM
Check th ucf file . you may not assigned proper pin to send the data to DAC.
You can generate the sinsoid using DDS core and send to DAC .
In this case you no need to use simulink
You may just use counter and assign output of counter to DAC for testing .
you must see ramp from DAC
06-10-2014 10:39 AM
Yes, I tried the UCF file. I am generating OBUFDS for four ports, which are of one bit width and they are generated fine!
I use OBUFDS for the data coming out of the fpga to DAC, which is 16 bit width. On opening .ncd file in FPGA editor, I found that the data pins are mapped to pins which are different from the UCF file given!
Also, these data pins only are not visible in the netlist/jtagcosim_top.ucf file generated!
Why could such a thing happen?
Thanks a lot,
06-10-2014 10:51 PM
If you are using 16bit width output then you need to specify 16 pin locations for the NMM ports.
Are you doing this?
Can you post the model and the UCF.
06-10-2014 11:14 PM
I was just about to post this update! For a change, last night, I just tried using 16 different pins and port mapped! That worked!!!
Earlier, when I did using 16 bit width buses - the .ncd file showed that the pins were getting mapped to some other LOCs.
06-10-2014 11:19 PM
I was able to solve the issue of generating differential ports for the DAC board. I tested by generating sine wave inside the FPGA ( using a LUT based DDS ), and sent it out to the DAC - I was able to obtain a sine waveform at the output of the DAC.
I am now trying to send a sine wave from Simulink to the FPGA to DAC board. But, I am not getting any waveform at the output of the DAC board. Anyone has any comments on what all things should I worry about in this simple implementation?
06-11-2014 02:12 AM
it might be that you are not using free running clock on the FPGA.
check this maybe it helps:
06-11-2014 08:18 AM
I don't know if it will help. Still I would like to attach the model I am using. And also, a screenshot.
In the model, I use sinewave source from Simulink -> Black Box (which generates sync, fifo_istr signals needed for dac, data_clk for dac, and latches the incoming data and sends out) -> NMM ports ( namely io_da15, io_da14... io_da0 ).
I also am taking the data output pins of the black box to a concatenate block, so that I can see the 16 bit data on a scope on the Simulink.
In the figure I am attaching, top plot = output of the concat block ; bottom plot = sine wave that goes into the black box!
The NMM ports have been port mapped to the DAC board pins, and I am not getting any waveform whatsoever on the output side of the DAC !
@s_aelsok : Hi Ahmed, I also tried free running clock. It did not have any effect.
Thanks a lot for any suggestions and help,