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poelslager

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06-18-2020 01:21 PM

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06-30-2017

Hi,

I am simulating a 16-bit 40 kHz signal out of the XADC at 1 Msps. I feed that into an FIR filter, then a fifo, and then a 1024 point FFT. The imaginary input on the xfft is all zeros. Finally, I put the FFT output into a CORDIC in translate mode.

I get a nice looking FFT plot in the simulator, but the peak is not where I expect. I am seeing more power in bin 43, but I would expect the peak to be in bin 41 or maybe 42.

What I get: (1 Msps / 1024) * (43-1) = ~41 kHz

What I expect: (1 Msps / 1024) * (41-1) = ~39 kHz

I'm not sure what is causing the different frequency in the FFT, does anybody have an idea of what I could check? Or is this result expected?

I've attached a plot of the simulator, clock is 200 MHz.

Thanks.

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poelslager

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06-22-2020 10:46 AM - edited 06-23-2020 09:03 AM

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Registered:
06-30-2017

~~I ran the simulation text file through an FFT using python and got the same results, so I think the problem is in the simulation data generated by the xadx IP. Thanks for the help.~~

I found the cause of the problem. The ADC is not running at 1 MHz, it is running at 961.54 kHz. Using the actual sample rate makes all the math work out as expected.

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markg@prosensing.com

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06-19-2020 03:01 AM

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01-22-2015

Try bypassing the FIR filter, or using a different FIR filter to see what effect it has on the FFT-produced spectrum.

Mark

poelslager

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06-19-2020 08:41 AM

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06-30-2017

Thank you for the suggestion. I removed the FIR filter. I had to drop the least significant bit out of the ADC and add a zero for the sign bit to get a good result. So the signal path is now: Simulated XADC -> FIFO -> FFT -> CORDIC

Unfortunately the power is still showing up in bin 43, see the attached image.

Any other suggestions? It seems like this should be really simple and straight-forward thing, so I'm sure I'm overlooking something simple. I just don't know what...

I can share the project if anyone wants to look at it, but I might need some instruction in packaging it up with the FIFO IP that I made.

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poelslager

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06-19-2020 08:52 AM

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markg@prosensing.com

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06-20-2020 10:43 AM

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01-22-2015

I agree that this appears to be a “front end” problem. That is, not only is the peak frequency bin in the wrong place, the peak also seems too broad (ie. spilling too much into other bins)

Try saving the digital outputs of the XADC to a file and then plotting them. You should see there are exactly 25 sampling intervals for one period of the 40KHz sinewave signal. If not, then the XADC sampling frequency is off or the analog input is not 40KHz.

If the above test does not uncover problems then use HDL to directly generate the digital samples for a 40KHz sinusoid and feed these directly into the FFT core.

The previous test may be especially useful since it will isolate the problem to either the front-end or back-end of your digital receiver.

poelslager

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06-22-2020 10:46 AM - edited 06-23-2020 09:03 AM

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Registered:
06-30-2017

~~I ran the simulation text file through an FFT using python and got the same results, so I think the problem is in the simulation data generated by the xadx IP. Thanks for the help.~~

I found the cause of the problem. The ADC is not running at 1 MHz, it is running at 961.54 kHz. Using the actual sample rate makes all the math work out as expected.

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