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Observer aviblanka71
Observer
640 Views
Registered: ‎11-21-2018

Use different AXI4-lite clock in system generator

I am working with Vivado 2016.4, I have  IP which implemented in system generator.

I've set the Implementation Interface on the Xilinx gateway blocks to "AXI4-Lite" which gives me the interface, however it is clocked at the same clock rate of data generator (40 MHz). I want to separtae the clock for in/out gateway, Is there anyway I can separate the clocks in system generator so that I can run the AXI4-Lite interface at 100-200MHz. while I run the waveform generation at 40 MHz? 

I tried to work with multiclock domain but it doesn't work? I tried to intrface the gate way to AXI4-Stream to have read the register faster.

I don't see on the system generator "AXI4-Stream" in "Interface Option" is not present

 

AXI4-Stream not found.png

 

How to enable "AXI4-Stream" Gateway in/out ?

Please advise, 

Thank you in advance,

Avi 

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4 Replies
Moderator
Moderator
596 Views
Registered: ‎08-16-2018

Re: Use different AXI4-lite clock in system generator

You can separate the clock in SysGen. For that you need to create different subblocks and put the SysGen-token in each subblock with required frequency. 

 

Please refer to Lab 4 of UG948

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug948-vivado-sysgen-tutorial.pdf

 

 


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Observer aviblanka71
Observer
568 Views
Registered: ‎11-21-2018

Re: Use different AXI4-lite clock in system generator

Hi, 

I tried this option i separated the clocks on for the logic and one for the register i got errors when i passed the signal with fast

clock to the block with slower clock, I got error during the compilation. 

I tried another method to use up-sample and down-sample for this signals, still have a errors

Thank you,

Avi 

 

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Xilinx Employee
Xilinx Employee
463 Views
Registered: ‎09-18-2018

Re: Use different AXI4-lite clock in system generator

Hello @aviblanka71 ,

Is this problem resolved ? If not, can you share the design for this case ?

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Scholar brimdavis
Scholar
444 Views
Registered: ‎04-26-2012

Re: Use different AXI4-lite clock in system generator

@aviblanka71   "Is there anyway I can separate the clocks in system generator so that I can run the AXI4-Lite interface at 100-200MHz. while I run the waveform generation at 40 MHz"

To my knowledge, Vivado SysGen always uses the *same* clock for AXI4_LITE gateways as the subsystem in which the gateway is instantiated.

The usual way to handle this in the higher level design is to clock those ports of the AXI Interconnect from the SysGen subsystem clock, and let the AXI interconnect handle the clock domain crossing. (Which unfortunately will not speed up the AXI interface as you are trying to do)

I would suggest using the SysGen multirate support[1], with the SysGen subsystem input clock running at 160 MHz, and the sample rate of your datapath at 40 MHz. ( The rate decimation is done either by changing the Gateway sample period, or with a rate changing block like 'Down Sample' ; e.g. if 'Simulink System Period' is set to the default of 1, set the Gateway 'Sample Period' to 4 ).

> How to enable "AXI4-Stream" Gateway in/out ?

AXI Stream interfaces in the SysGen IPI catalog flow are supported by inference from the suffixes of gateway names. See UG897 (v2018.3) page 200:

 

sysgen_axis.png

 

 

 

 

-Brian

[1] Multirate overview is on page 30-33 of  UG897 (v2018.3) , in particular the 'Synchronous Clocking' section on page 32

Multirate in SysGen can be confusing if you haven't used it before, I usually turn use the sample time coloring option in SysGen to highlight the rate changes.

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