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Adventurer
Adventurer
10,527 Views
Registered: ‎02-18-2014

Using IBUFDS for differential signals in Hardware co simulation via JTAG

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Hi,

 

 I am implementing a system in which a sine wave source is generated from Simulink, sent to FPGA ( blackbox having buffers and sync signals needed for DAC), and then sent to a DAC board which takes in differential data, sends out differential clock to the FPGA

 

The black box, I have implements a differential to single ended buffer for the clock ( coming from DAC to FPGA ). For this, I have a NMM port (mapped from DAC clk output to FPGA input).

 

But, the issue is NMM port itself generates a IBUF ( I have a fpga_clk_p and fpga_clk_n ) and my black box calls another IBUFGDS ! And this generates an error ! How do I get over this issue ?

 

" Buffers of the same direction cannot be placed in series "

 

So, how do I get over this issue ?

 

Thanks in advance,
Basil.

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1 Solution

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Adventurer
Adventurer
16,141 Views
Registered: ‎02-18-2014

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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UPDATE:

 

Hi,

 

 I do not know if this is a perfect solution. But, due to great help from a fellow user, Ahmed, I was able to generate differential buffers for the Non Memory Mapped Ports that are generated! I could generate IBUFDS and OBUFDS buffers for the ports, though I could not use IBUFGDS buffer for a clock input that I am sending to the fpga from another device (DAC) !

 

Well, steps I used:

1. Remove all buffers put for the input and output pads (because you can provide buffers in the top module ) from your blackbox module

2. Create New Compilation Target
3. Add non memory mapped parts ( just give the single ended names : say, if you have port_p and port_n ; just give "port" as the name of your NMM port )
4. Save Zip and Install plugin to generate the library containing the ports.

5. In the UCF in /sysgen/plugins/compilation/Hardware Co Simulation/"yourboardname"/"yourboard".ucf : Edit the pins from "port" to "port_p". You may also add "port_n" and its corresponding LOC

6. Copy the NMM ports from the library to your model, and select each and "look under mask". Click on the "gateway in/gateway out" block and on the MATLAB window : type :
             -- a.   dump(xlGetPortParams('gcbh'))

                          -- This will display the port parameters of the selected gatway in/out block
             -- b.   xlSetPortParams(gcbh, 'IOType', 'obufds')

                         -- This will set the buffer type to OBUFDS. You can give whichever buffer you would like as parameter.
7. Open the Sys Gen token, and click on Generate.

 

Now, your "jtagcosimtop.vhd" file is generated : which has automatically used "port_p" and "port_n" at top level, sent it through the buffer you mentioned in step 6, and then to your blackbox.

 

Thanks all, especially Ahmed @s_aelsok  for the help on this!


In case, anyone finds out : 1. any error in what I did,
2. Any way to give IBUFGDS

Please inform me too.

 

Thanks,
Basil

 

View solution in original post

10 Replies
Xilinx Employee
Xilinx Employee
10,521 Views
Registered: ‎09-20-2012

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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Hi Basil,

 

Disable the IO buffer insertion for the ports  fpga_clk_p and fpga_clk_n using buffer_type attribute.

 

Refer to page-387 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf for details on usage of attribute. Set this attribute to "none" for the ports which are connected to IBUFDS in the black box instance.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Adventurer
Adventurer
10,512 Views
Registered: ‎02-18-2014

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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Hi Deepika,

 

 Thank you for replying. Where exactly do I disable this attribute? Do you mean to say that, I should do it in the .vhd code generated ? Say, my simulink .mdl file is "mysimulink". Thus, I get a "mysimulink.vhd" and "mysimulink_cw.vhd" files generated.

 

 Should I make the change in the "mysimulink.vhd" file, in order to disable buffer_type ?

 

Thanks,

Basil.

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Xilinx Employee
Xilinx Employee
10,509 Views
Registered: ‎09-20-2012

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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Hi Basil,

 

I think you can disable it in mysimulink.vhd file

 

or 

 

you can write the attribute in top module where you instantiated this mysimulink.vhd file.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Adventurer
Adventurer
10,500 Views
Registered: ‎02-18-2014

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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Hi Deepika,

 

 I tried changing the attributes in the /myworkfolder/netlist/mysimulink.vhd & in the /myworkfolder/netlist/mysimulink_cw.vhd files!

 

But, once I click on Generate in the Sys Gen token, the same error reappears, and i see that both the .vhd files are just the same as earlier! (.i.e the unchanged ones!)

 

Any idea how could I get over it?

 

Thanks,

Basil

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Adventurer
Adventurer
10,488 Views
Registered: ‎02-18-2014

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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Hi,
I learnt that from the sysgen user file, I could give my own top level .vhd file by setting in "yourboard_postgeneration.m". But, I also have to give a "yourboard_toplevel.ngc" file and "foo.edf" file! I understand that, I could synthesize my "yourboard_toplevel.vhd" file, and get "yourboard_toplevel.ngc" file.

 

But, what is this "foo.edf" file ?

 

Thanks,
Basil

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Adventurer
Adventurer
10,474 Views
Registered: ‎02-18-2014

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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Hi,


 It would be great if I could get any help on how to do this change of attribute! From what I understand, whatever change I make in the toplevel .vhd file "jtagcosim_top.vhd" , on clicking the "Generate" button, a new jtagcosim_top.vhd is generated on compilation and, that file is used further.

 

 Thanks in advance,
Basil.

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Adventurer
Adventurer
10,463 Views
Registered: ‎02-18-2014

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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I came to from a fellow user on this forum, that I could try to change the parameters of the ports, using xlGetPortParams, xlSetPortParams(gcbh, 'IOType', 'ibufds') .

 

I did not have much success with it. If anyone could help me with the above, or else, any other solution - it would be really great.

 

Thanks,
Basil.

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Highlighted
Adventurer
Adventurer
16,142 Views
Registered: ‎02-18-2014

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

Jump to solution

UPDATE:

 

Hi,

 

 I do not know if this is a perfect solution. But, due to great help from a fellow user, Ahmed, I was able to generate differential buffers for the Non Memory Mapped Ports that are generated! I could generate IBUFDS and OBUFDS buffers for the ports, though I could not use IBUFGDS buffer for a clock input that I am sending to the fpga from another device (DAC) !

 

Well, steps I used:

1. Remove all buffers put for the input and output pads (because you can provide buffers in the top module ) from your blackbox module

2. Create New Compilation Target
3. Add non memory mapped parts ( just give the single ended names : say, if you have port_p and port_n ; just give "port" as the name of your NMM port )
4. Save Zip and Install plugin to generate the library containing the ports.

5. In the UCF in /sysgen/plugins/compilation/Hardware Co Simulation/"yourboardname"/"yourboard".ucf : Edit the pins from "port" to "port_p". You may also add "port_n" and its corresponding LOC

6. Copy the NMM ports from the library to your model, and select each and "look under mask". Click on the "gateway in/gateway out" block and on the MATLAB window : type :
             -- a.   dump(xlGetPortParams('gcbh'))

                          -- This will display the port parameters of the selected gatway in/out block
             -- b.   xlSetPortParams(gcbh, 'IOType', 'obufds')

                         -- This will set the buffer type to OBUFDS. You can give whichever buffer you would like as parameter.
7. Open the Sys Gen token, and click on Generate.

 

Now, your "jtagcosimtop.vhd" file is generated : which has automatically used "port_p" and "port_n" at top level, sent it through the buffer you mentioned in step 6, and then to your blackbox.

 

Thanks all, especially Ahmed @s_aelsok  for the help on this!


In case, anyone finds out : 1. any error in what I did,
2. Any way to give IBUFGDS

Please inform me too.

 

Thanks,
Basil

 

View solution in original post

Visitor dongdavis
Visitor
7,578 Views
Registered: ‎07-15-2015

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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I did according to what you said step by step. And at the step 6, I set the block Annotation "IOType=%<obufds>" in the "properties...". And there is no error:770 anymore.

 

Thanks a lot! Your solution maybe the only one. 

 

My software version is ISE 14.7 & Matlab 2012b. 

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Observer nwpu310
Observer
5,967 Views
Registered: ‎08-25-2015

Re: Using IBUFDS for differential signals in Hardware co simulation via JTAG

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1.have you figure out the solution to use IBUFGDS buffer for a clock input that I am sending to the fpga from another device (DAC)?

2.can the clock from DAC drive BUFIO/BUFR/OserDes or MMCM in a Virtex6 device? 

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