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noelpedro
Observer
Observer
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Registered: ‎12-26-2018

Using XFFT 9.0 Data from ADI's UTIL_FIR_DECIMATOR

Hi all,

 

My set up is that I'm Downsampling data from ADC from 40msps to 2msps Further more I'm streaming the data to XFFT ip core. Now The problem that I'm having is that the data that streams out of fir decimator is at a rate of 40MHZ however the valid signal is toggle ling high then low after every 20 clock cycles. It seems like the FFT corr likes the valid signal to stay high for the respective clock rate??

 

Note I have a custom module that latches the data because I'm zero padding.

 

Heres what I have tried:

configured fft with 40mhz clock throughput and made it real time: result the FFT is executed too soon it dosent wait for all 8192 samples it used the first 8192 samples with respect to the 40MHZ clock which is bad because the FIR is only valid during a 20th of the 8192 samples.

Configured it 2Mhz throughput clock: same result as above.

 

Configured FFT to be non real time with 40Mhz throughput clock: result the data didnt consistently stream

out of the fft.

 

Any insight is appreciated.

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nathanx
Moderator
Moderator
465 Views
Registered: ‎08-01-2007

You are correct that FFT core wants the valid signal to stay high for every clock cycle.

If the valid output is only asserted every 20 cycles, you can use a FIFO to store the valid data, the valid signal can be used as the write enable of the fifo. The FIFO output can output valid continuous data to FFT IP core.

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