Using of Dual Port RAM

[evgenia89]

Hello!

Can anyone explain me how to use the block Dual Port RAM in Simulink? I am especially confused with meaning of ports addra and addrb.

Thanks!

Evgenia.

[vlavruhin]

Hello, Evgenia.

Dual Port RAM is ordinary RAM block with two access input/output ports: port A and port B. So you can independently access to common memory space through these two ports. For example, you can have concurrent reading of one memory cell using port A and writing of other memory cell using port B.

AddrA is address line of port A. AddrB is address line of port B.

There is a detailed description of Dual Port RAM block in System Generator Reference Guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sysgen_ref.pdf

[evgenia89]

Hello, Vitaly,

I applied sine waveform to addrb port, then I sum two signals from A and B and apply this to addra port.
I choose with the help of MCode, when wea and web are enable:
if x < 1000
    z = true;
  else
    z = false;

The result is not what I expected...

[vlavruhin]

Evgenia, what are your expectations?

How are Counter, Counter1 and Dual Port RAM blocks configured ?

What are initial values of the counters? If initial values are equal, then you will get write-write collision (simultaneous write attempt at same memory cell, which will result in NaN output).

[evgenia89]

I expected increasing of the signal amplitude every cycle.

Configurations are:
RAM: Port A - read before write, port B - read after write;
Counter: initial value - 0, up to 1000;
Counter1: initial value - 1000, up to 2000;
Counter2: initial value - 0, up to 2000.

[vlavruhin]

Ok, Evgenia.

What are parameters of 'AddSub' block?

What is at output of your model? Could you attach MDL file?

[evgenia89]

Vitaly,

thank you for your patient, all the parameters are in the attached file.

Evgenia.

[vlavruhin · Accepted solution]

Am I right that the bitwidths of counters are 8 bit? I.e., the counter is able to count from 0 to 255 and can't reach value 1000.

[evgenia89]

Vitaly, thank you for your help very much. I checked the bitwidths and modified the model and now it works ok.

But now I need to modify the model because I want to divide the AddSub output signal to 2 and apply it to dina port of Dual Port RAM. The problem is that i need to divide from the second cycle, because during the first cycle port A output is empty.

I am using MCode block. The MatLab code is following:

function z = divst(x, i);
if (i < 512) 
    z = x;
else
    z = xl_force(x, xlSigned, 11);
end

When I start simulation I get a message: 'Illegal type of port dinb', because output of the block MCode has type Fix_17_11 while I was expecting Fix_16_11.

Also I am wondering what block I can use for variable i. For now I put counter, but I understand that it is not good solution.

Best regards,
Evgenia.

[vlavruhin]

Hello, Evgenia.

If you would like to divide samples by 2, if some condition is true, and do not divide if this condition is false, then you should shift bits of these samples.

Lets assume, you have 16 bits (at input and output): b15, b14, ..., b1, b0.

1) If you wouldn't like to have division, then output samples should be as input: out15 = in15, out14 = in14, ..., out1 = in1, out0 = in0.

2) If you would like to divide by 2, then output samples should be shifted: out15 = in15, out14 = in15, ..., out1 = in2, out0 = in1. And in0 sample should be dropped in that case.

The function xl_force() does nothing with samples. It just sets properties of data type in such manner, that Simulink knows that these samples should be interpreted differently (different data type, different binary point, and hence different range of decimal values).

So in your model, you should actually shift bits of samples in one case, and do not shift otherwise. To do it, use function xfix({xlSigned, 16, 10}, x) and xfix({xlSigned, 16, 10}, x/2).

---

evgenia89 wrote:

Also I am wondering what block I can use for variable i. For now I put counter, but I understand that it is not good solution.

---

Why not? You need to implement a delay. So one option is to use a counter, and other is to have a series of registers (but it's huge solution for long delay). Just make sure that your counter will stop after the condition is met.

[evgenia89]

Hello, Vitaly,

I implemented division with Divider Generator. Now I have a problem with compilation: the process Map takes about 2 hours if I include my model to the project (normally it took about 20 minutes). What can be a reason for so long mapping?

My Simulink model is attached.

Function precision is:

function z = precision(x)
    z = xl_force(x, xlSigned, 0);
end

 Function back_precision is:

function z = back_precision(x) 
    z = xl_force(x, xlSigned, 10)
end

 Function xlmax is:

function z = fifo_reset(x)
  if x == 511
    z = true;
  else
    z = false;
  end

Best regards,

Evgenia.

[vlavruhin]

Hello, Evgenia.

Well, your project is getting bigger.

Do you implement moving average filter for I/Q noisy signal? If so, then there are simpler ways to do it.

Also you can substitute MCode blocks by Reinterpret block ( for precision and back_precision functions) and Relational block (for xlmax function).

[evgenia89]

Hello, Vitaly.

Yes, I implement a moving average filter.
The description of Reinterpret block says that this block costs nothing in hardware. Can I still use it?

Best regards,

Evgenia.

[vlavruhin]

---

evgenia89 wrote:

The description of Reinterpret block says that this block costs nothing in hardware. Can I still use it?

---

Yes, you can. It costs nothing in hardware, because this block just says to System Generator to interpret that N-bits bus as number with binary point of your choice. But data samples are not altered in that case.

[evgenia89]

Hello, again!

The filter I am trying to implement is now working perfectly during simulation. But after FPGA configuration the output signal looks completely different from the input one. What can be a reason of this difference? And what can I do in this case?

Thank you for your help,

Evgenia.

[vlavruhin]

Hello.

---

The filter I am trying to implement is now working perfectly during simulation. But after FPGA configuration the output signal looks completely different from the input one. 

---

Could you describe your hardware setup? Are you trying HW-cosimulation? Are the inputs feeded from other FPGA blocks or from external hardware (ADC)? What is your sysgen clock? Software simulation of model is behavioural simulation only, i.e. it doesn't take into account all real route delays in FPGA. Make sure that you have defined all constraints properly.

[evgenia89]

Thank you for you quick response!

I am using ML605 with FMC150 daughter card.
I didn' try HW-cosimulation, I included the model to my main project and downloaded this to FPGA.
The inputs are feeded with FPGA blocks which are connected to ADC.

The FPGA clock in SysGen is 10 ns.

The signal I applying to ADC is ~100MHz.

I thought that it can be because I apllied the data type Unsigned_16_10 to GatewayIns and then I also reinterpret the data. But I have no idea how I can get to know which data type is in the signal after ADC.

Best regards,
Evgenia.

[chirag1@]

Hello every one,

I am using a dual port ram for storage of sine wave .Whenever we simulate the data will be stored and read from port B till this its working fine but we need following things.

1]I need to access the data in RAM . This is possible???

2]I will discontinue the data given to ram and i need to get data stored in RAM. How to achieve it????

Thanks and regards,

chirag

[balkris]

You may use ROM if you only want to to write once and read sine way sample. In case you want multiple sine way you can store multiple sample and read which one you want to required to read.

[G7]

Hi

Could you help me on how to read and write an image from the dual port RAM. I have attached a screenshot of what I've done. I am getting a black screen on the video viewer 2.

Thanks