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02-05-2011 03:47 AM
03-08-2011 06:24 AM
Q. as it works in microblaze why do you need to implent it in vhdl?
Q. Have you simulated this?
I would use the C code and set breakpoints to see what is going on and then comapre that with the HDL simualtion that you are doing. You are right in thinking about the conversion and wht they represent.
regards
Mike
03-08-2011 08:26 AM
05-19-2018 04:30 AM
I wrote the code and i got an error. These error as follows ;
WARNING:Xst:819 -One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<Error>, <Output>, <SetVal>, <Kp>, <Ki>, <Kd>
WARNING:Xst:653 - Signal <SetVal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000001000000111101011.
WARNING:Xst:653 - Signal <Kp> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000001010.
WARNING:Xst:653 - Signal <Ki> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000001.
WARNING:Xst:653 - Signal <Kd> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000010100.
WARNING:Xst:737 - Found 16-bit latch for signal <sAdc>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <inter>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <Error>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <d>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <p>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <DacDataCarrier>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:643 - line 55: The result of a 32x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
The VHDL code is on attachment.