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Visitor ituumitcelik
Visitor
8,783 Views
Registered: ‎02-05-2011

VHDL PID controller problem..

 

Hello,
I am trying to write a PID controller with a state machine. It is working but I think it is not working properly. 
I think there is a signed unsigned number or type conversion problem. Please, could you fixed it for me?
Is there any problem? When I tried the following algorithm in microblaze in C language, the PID module working properly. 
With best regeards,
entity PIDModule is
    Port ( ADC_DATA : in  STD_LOGIC_VECTOR (15 downto 0); --16 bit unsigned PID input
           DAC_DATA : out  STD_LOGIC_VECTOR (15 downto 0); --16 bit unsigned PID output 
           CLK1 : in STD_LOGIC;
);
end PIDModule;
architecture Behavioral of PIDModule is
    type statetypes is (Reset,
                              CalculateNewError,
                              CalculatePID,
                              DivideKg,
                              Write2DAC,                              
                              SOverload,
                              ConvDac
                              );                              
    
    signal state,next_state : statetypes := Reset;     
    signal Kp : integer := 10;
    signal Kd : integer :=20;
    signal Ki : integer :=1;
    signal Kg : integer := 256;
    signal Output : integer := 1;
    
    signal SetVal : integer := 33259; 
    signal sAdc : integer := 0 ;
    signal Error: integer := 0;
    signal p,i,d : integer := 0;
    signal DacDataCarrier : std_logic_vector (15 downto 0);
    signal AdcDataCarrier : std_logic_vector (15 downto 0);
    
begin
PROCESS 
      variable Output_Old : integer := 0;   
      variable Error_Old : integer := 0;
     BEGIN  
          IF CLK1'EVENT AND CLK1='1' THEN  
state <= next_state;
          END IF;
         case state is
                 when Reset =>
                        sAdc <= conv_integer(ADC_DATA);  --Get the input for PID
                        next_state <= CalculateNewError;
                        Error_Old := Error;  --Capture old error
                        Output_Old := Output;    --Capture old PID output
                    when CalculateNewError =>  --
                       next_state <= CalculatePID;
                       Error <= (SetVal-sAdc); --Calculate Error
                    
                    when CalculatePID =>
                        next_state <= DivideKg;
                        p <= Kp*(Error);              --Calculate PID 
                        i <= Ki*(Error+Error_Old);
                        d <= Kd *(Error-Error_Old);                     
                    when DivideKg =>
                        next_state <= SOverload;
                        Output <=  Output_Old+(p+i+d)/2048; --Calculate new output 
                       
                    when SOverload =>
                        next_state <=ConvDac;
                        if Output > 65535 then
                            Output <= 65535 ;
                        end if;     
                        if Output < 1 then 
                            Output <= 1;
                        end if;
                        
                    when ConvDac =>         
  --Send the output to port
                        DacDataCarrier <= conv_std_logic_vector(Output ,16);
                        next_state <=Write2DAC;
                        
                    when Write2DAC =>
                        next_state <= Reset;
                        DAC_DATA <= DacDataCarrier;
                end case;
            END IF;
                        
      END PROCESS;
end Behavioral;



 

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3 Replies
Xilinx Employee
Xilinx Employee
8,624 Views
Registered: ‎05-23-2008

Re: VHDL PID controller problem..

 

 

Q. as it works in microblaze why do you need to implent it in vhdl?

Q. Have you simulated this?

 

I would use the C code and set breakpoints to see what is going on and then comapre that with the HDL simualtion that you are doing. You are right in thinking about the conversion and wht they represent.

 

regards

Mike

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Teacher rcingham
Teacher
8,621 Views
Registered: ‎09-09-2010

Re: VHDL PID controller problem..

Your unnamed PROCESS will not simulate properly because it does not have a sensitivity list. Also, it is a ghastly hybrid between a 1-process and 2-process FSM implementation, which needs radical surgery.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Observer los_galacticos
Observer
1,158 Views
Registered: ‎02-17-2018

Re: VHDL PID controller problem..

I wrote the code and i got an error. These error as follows ;

 

WARNING:Xst:819 -One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<Error>, <Output>, <SetVal>, <Kp>, <Ki>, <Kd>

 

WARNING:Xst:653 - Signal <SetVal> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000001000000111101011.
WARNING:Xst:653 - Signal <Kp> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000001010.
WARNING:Xst:653 - Signal <Ki> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000001.
WARNING:Xst:653 - Signal <Kd> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000010100.
WARNING:Xst:737 - Found 16-bit latch for signal <sAdc>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <inter>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <Error>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <d>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <p>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <DacDataCarrier>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 

WARNING:Xst:643 -  line 55: The result of a 32x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.

 

 

The VHDL code is on attachment.

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