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Observer nagender_patel
Observer
1,692 Views
Registered: ‎03-21-2017

VIvado system generator sample time error uint32

hello

i have  taken a simple sine wave in simulink (xilinx sysgen) 

frequency 1khz

sample time 200usec

 

blocks are arranged as shown below

 

i am getting the error

 

The periodic sample time 1000000.0 is not allowed because the ratio of this sample time over base rate (0.0002) is greater than the maximum value of uint32.

sysgen.png
sysgen_error.png
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4 Replies
Observer nagender_patel
Observer
1,634 Views
Registered: ‎03-21-2017

Re: VIvado system generator sample time error uint32

can anyone please reply to solve this error

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Xilinx Employee
Xilinx Employee
1,590 Views
Registered: ‎08-02-2011

Re: VIvado system generator sample time error uint32

Use relative rates by normalizing the simulink sample period to the hardware clock rate settings.
www.xilinx.com
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Visitor sagar
Visitor
289 Views
Registered: ‎03-25-2019

Re: VIvado system generator sample time error uint32

please any one to help for fft simulation in vivado??

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Moderator
Moderator
272 Views
Registered: ‎08-16-2018

Re: VIvado system generator sample time error uint32

Please reduce the sample time which is specified as "1000000.0" or go to system-generator token and change the frequency there. It will remove the error.


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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