06-24-2021 11:59 AM
I am still new to FPGA development and hopefully someone can suggest me a right way to solve the problem I have.
I created a custom IP core for a signal processing system using Matlab/Simulink HDL coder and now I am testing the PL design using in Vivado 2018.3.
The operation of the IP core was validated in Matlab/Simulink environment and IP core was properly generated for Zynq-7000 chip. As you can see, all ports are AXI-stream interface and some signal data from each channel is fed in the custom IP. After processing the data in this block, this IP spits out the detection data again with AXI-stream so that I can record the detection data via DMA.
Next, I made a simple test bench in Verilog in Vivado to simulate the behavior to validate the operation in Vivado environment.
For input side, TVALID goes high after first data (f0ff: just random number I picked) goes in, so I guess input side of behavior seems to be correct.
However, TREADY remains "X" and TVALID remains "0" for all 4 outputs. Also, TLAST of one of output stays "Z" and other 3 turn 0 after a few tens of nano seconds. I think this behavior is wrong because TREADY and TVALID should become both "1" at some point to transfer data through AXI Stream interface.
I tried to get some data from this IP using simple DMA, but no data was transferred to DDR, probably because of this strange behavior.
I have several questions.
1. Is there any good tool for me to further debug the IP core in Vivado? IP seems to be working in Matlab/Simulink environment, so I don't know what could be wrong.
2. This IP is relatively slow due to the amount of signal processing and actually did not meet the timing constrains when I create the whole PL project using this IP. Can this strange behavior related to this timing issue even for behavior simulation? For this test bench, I am using 100MHz clock and PL project has a few 10 ns of slack.
3. Any other potential cause of this behavior? Any suggestion is appreciated at this point.
Thank you very much for your help in advance.
06-27-2021 11:23 PM
I got confused about the TREADY and TLAST and actually TREADY for AXI-Stream Master port is input from downstream IP core, so it make sense that it was "X" without initial value setup. With right initial value, I can see it is hold 1. I still don't understand why TLAST from one of output ports stays "Z" and other three goes to "0", but I think it is not important here. I believe IP core itself is operating properly.
Next, I tried to connect this custom IP core in IP integrator to test the signals with ILA while running simple interrupt DMA example. I used TVALID from DMA S_AXIS_S2MM port as a trigger, but no signal was captured while running DMA. I also tied TVALID of one of input channels (AXI-stream Slave port) of this custom IP as a trigger, but no signal from DMA was captured either. Output from ADC connected to the custom IP can be seen using ILA with immediate capture mode, so HW and ILA are working for sure, but no signal is coming from DMA.
Custom IP itself seems to be working, but PL project using this IP is not. Is there any way to validate the PL project? I am kind of stuck here and I don't really know what I can do to solve this situation.
Any suggestion is appreciated.