06-08-2017 09:19 AM
According to the Xilinx documentation this IP core comes as Encrypted RTL. Can anyone elaborate on what exactly is encrypted about the RTL?
Ideally I want to purchase the core and have full access to the RTL (preferably VHDL) source code.
I would be grateful if anyone who has experience with this core could please elaborate?
06-08-2017 09:52 AM
When you generate the IP, you generate encrypted VHDL / Verilog (depending on the project settings). You won't have access to the RTL (i.e. you can open the file, but you won't be able to uderstand anything, this is the meaning of encrypted)
06-09-2017 02:35 AM
To be honest I have never created a post on the forum... So I don't know ;-)
I guess you use the "option" link on the post you want to mark as good answer and then mark it as solution.
06-09-2017 08:20 AM
06-11-2017 11:53 PM
It will be the encrypted ( obfuscated) VHDL. Vivado will put the file has read only as it is encrypted.
06-22-2017 03:00 AM
We used to provide an example on how to use VHDL to write convolution encoder (7 years ago), but I haven't heard anything like this for Viterbi Decoder.
It's better to contact FAE. If you don't have FAE, please contact Authorized Distributors (see the contact info in the link below), and explain what you need :