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uc269
Newbie
Newbie
2,113 Views
Registered: ‎05-17-2016

Viterbi Decoder v9.1

According to the Xilinx documentation this IP core comes as Encrypted RTL.  Can anyone elaborate on what exactly is encrypted about the RTL?

 

Ideally I want to purchase the core and have full access to the RTL (preferably VHDL) source code.

 

I would be grateful if anyone who has experience with this core could please elaborate?

 

Thank you.

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6 Replies
florentw
Moderator
Moderator
2,104 Views
Registered: ‎11-09-2015

Hi @uc269,

 

When you generate the IP, you generate encrypted VHDL / Verilog (depending on the project settings). You won't have access to the RTL (i.e. you can open the file, but you won't be able to uderstand anything, this is the meaning of encrypted)

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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uc269
Newbie
Newbie
2,066 Views
Registered: ‎05-17-2016

Thank you @florentw,

 

I'm new to this forum.  Can you please tell me how I mark an answer as "Accept as solution"?

 

Many thanks.

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florentw
Moderator
Moderator
2,063 Views
Registered: ‎11-09-2015

Hi @uc269,

 

To be honest I have never created a post on the forum... So I don't know ;-)

 

I guess you use the "option" link on the post you want to mark as good answer and then mark it as solution.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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uc269
Newbie
Newbie
2,053 Views
Registered: ‎05-17-2016

@florentw,

 

Thank you for your reply, can I clarify your previous answer?

 

When you say that I can open the file, will it be obfuscated VHDL that I will be reading or something else?

 

Thank you. 

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florentw
Moderator
Moderator
2,018 Views
Registered: ‎11-09-2015

Hi @uc269,

 

It will be the encrypted ( obfuscated) VHDL. Vivado will put the file has read only as it is encrypted.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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xud
Xilinx Employee
Xilinx Employee
1,912 Views
Registered: ‎08-02-2007

We used to provide an example on how to use VHDL to write convolution encoder (7 years ago), but I haven't heard anything like this for Viterbi Decoder.

 

It's better to contact FAE. If you don't have FAE, please contact Authorized Distributors (see the contact info in the link below), and explain what you need : 

https://www.xilinx.com/about/contact/authorized-distributors.html

 

 

 

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