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345 Views
Registered: ‎03-07-2019

Viterbi Decoder

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Hi ,

I would like to decode 500 (encoded by a convolution encoder with 1 / 2 rate and a constraint length of 7) bits by using Viterbi decoder (IP core) to get 250 bits output. 

Configuration of the Viterbi Decoder IP core in the Block Design:

Standard Viterbi Type, Constraint Length 7, Traceback length 96, Parallel Architecture, Best State is not used, No Puncturing, Hard Coding, convolution codes are (1011011 and 1111001), BER symbol count is not used.

I want to write a function in C. Each time I call this function, It decodes 500 bits by using Ip core to get 250 bits output. 

     - However I do not know how many bits I will give the viterbi decoder to get outputs I desired.

     - I do not know how I will use aresetn, tvalid signals.

     - for s_axis_data_tdata there are two bits for rate 2. Is DATA_IN0 and DATA_IN1 1.and 8. bits,respectively?

Many thanks in advance.

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Moderator
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311 Views
Registered: ‎08-01-2007

回复: Viterbi Decoder

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     - However I do not know how many bits I will give the viterbi decoder to get outputs I desired.

A: see the "implementation details" tab of Viterbi decoder GUI. 

     - I do not know how I will use aresetn, tvalid signals.

A: see PG027 -Viterbi decoder IP PG.

     - for s_axis_data_tdata there are two bits for rate 2. Is DATA_IN0 and DATA_IN1 1.and 8. bits,respectively?

A: see the "implementation details" tab of Viterbi decoder IP GUI. 

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Moderator
Moderator
312 Views
Registered: ‎08-01-2007

回复: Viterbi Decoder

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     - However I do not know how many bits I will give the viterbi decoder to get outputs I desired.

A: see the "implementation details" tab of Viterbi decoder GUI. 

     - I do not know how I will use aresetn, tvalid signals.

A: see PG027 -Viterbi decoder IP PG.

     - for s_axis_data_tdata there are two bits for rate 2. Is DATA_IN0 and DATA_IN1 1.and 8. bits,respectively?

A: see the "implementation details" tab of Viterbi decoder IP GUI. 

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299 Views
Registered: ‎03-07-2019

回复: Viterbi Decoder

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 - I do not know how I will use aresetn, tvalid signals.

A: see PG027 -Viterbi decoder IP PG.  I searched and I found how to do it.

     - for s_axis_data_tdata there are two bits for rate 2. Is DATA_IN0 and DATA_IN1 1.and 8. bits,respectively?

A: see the "implementation details" tab of Viterbi decoder IP GUI.  I searched and I found yhe answer.

Thanks.

 

 - However I do not know how many bits I will give the viterbi decoder to get outputs I desired.

A: see the "implementation details" tab of Viterbi decoder GUI. Still I do not know this. Please Can you send a sceenshot of it? In my opinion, viterbi decoder  operates on continuous bit stream. I have to know the starting and finishing points of the trellis.Because I dont want to operate it as continuous bit stream. Am I correct?

Each time I call my function, viterbi decoder will decode 500 bits to get 250 bits. I put the input as  500 + traceback lenght , it did not work. I put the input as  traceback lenght + 500 + traceback lenght , It did not work. 

Thanks in advance. 

  

 

 

 

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Moderator
Moderator
282 Views
Registered: ‎08-01-2007

回复: Viterbi Decoder

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Can you accpet the reply as the solution if it answers your question?

It's better if you can put the different questions in different topics.

For block decoding of Viterbi, see XAPP551.

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263 Views
Registered: ‎03-07-2019

回复: Viterbi Decoder

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I will see. Thanks for you advices.

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