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Observer
Observer
337 Views
Registered: ‎02-26-2020

Vitis HLS cannot generate System Generator IP

Hi to all

I am trying to generate system generator block using Vitis HLS environment, but nothing happens. The HLS block in system generator can't find the design made in Vitis HLS.

Please help, this task is fulfilled when I use Vivado_hls

Thanks

Michael

 

2 Replies
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Xilinx Employee
Xilinx Employee
304 Views
Registered: ‎12-14-2017

Hi,

Thank you for bringing up this

Unfortunately, we do not have a support to import Vitis_HLS project in to Sysgen in 2020.1. Vivado HLS block in sysgen library is used to import only Vivado HLS project but not Vitis HLS project. 

You will see the support in the next release

Regards,

Raju A.

 

Observer
Observer
233 Views
Registered: ‎02-26-2020

Hello Raju A.

As I understood Xilinx  exchanged the VIVADO HLS tool by a new  Vitis HLS tool in version 2020.1 without supporting it's full functionality. In my opinion based in more than 40 years of system engineering work this is absolutely unprofessional. 

Regards

Michael

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