02-17-2020 03:29 AM
I have been using Vivado 2019.1 with TRD design zcu106_audio in a xcz4ev device. When I port this design to 2019.2 Vivado uses 1000+ more LUTs causing an overflow of resources. All settings are the same. I also tried to increase optimization effort without success. This is strange as I don't expect layout efficiency to get worst with newer versions.
02-26-2020 06:31 AM
Hi @mstamler3037 ,
This is possible when moving between versions due to changes in optimisations, versions of an IP etc.
Does the design still meet timing post implementation?
02-26-2020 09:52 PM
Hi. Thanks for your reply. The design formally does not meet timing but the issues are very minor that can be cleared up with simple constraints.
The differences in size is on the order of thousands of LUTs. This is very surprising. I have tried different strategy settings but there is no change. Any ideas?
02-27-2020 08:41 AM
Have a look at the synthesis logs and run the report utilization reports. Both of these break down the primitive usage and with them you may be able to isolate where the LUTs are coming from. It is possible that something like a Memory / DSP or a Multiplier is now being synthesized using LUTS instead.
Check the utilisation post synthesis, after opt_design, place_design to see where the designs diverge.
If you have added / removed certain constraints such as DONT_TOUCH this may have had an effect.
Check the messages, the Critical Warnings etc for the stage that has changed as this may give further information.
If you don't see anything obvious then we can look at the synthesis and implementation logs from the two runs to see if anything stands out.