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Newbie moyeretzian
Newbie
6,517 Views
Registered: ‎03-03-2010

Weird "View HDL Instantiation Template" Error

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Hello!,

 

I'm trying to get a very basic Simulink model (a counter) to compile, and work on my Spartan-3E FPGA, but am having a problem.  It's probably a simple issue that I'm overlooking, but I can't figure it out.

 

I created a basic counter in Simulink from the Xilinx blocket (did not add synchronous reset or enable, for simplicity).  On the output of the counter I put a "gateway out".  On the output of the gateway out I put a scope (to make sure sure it counted correctly).  After that I put the "System Generator" block in the bottom right corner.  I put in my model FPGA, Compilation: HDL Netlist, Synthesis Tool: XST, HDL: Verliog (same as my ISE project).  I pressed OK, saved my Simulink model, and generated the code through the System Generator block.

 

In ISE, I had a project created that uses the same model FPGA and Verilog code (same as I specified in Simulink System Generator block).  I created a "counter_top" module so I could instantiate the system generator file.  I then added the ".sgp" source file into my project.  Everything is fine up until this point (no errors or anything that I could see).   I click on the .sgp file that is generated, and in the bottom left there is an option to "View HDL Instantiation Template."  I double click on this, and it gives me an error "To use this file in your design, insert the file 'false' in the source file which instantiates the module".

 

This error is really confusing.  A day or so ago I actually got it working magically (I have no idea what I did).  Thinking that I had fixed what was wrong, I changed something on the Simulink model and it stopped working again.

 

If you need more info on a certain parameter, let me know and I will let you know.  Also, I've been following the same steps as shown on the video "ISE_SysGen_Integration" from the Xilinx website, but, like I said, am stuck on this specific step.

 

Help is much appreciated.

 

Thanks,

-Mike

 

 

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Newbie moyeretzian
Newbie
6,801 Views
Registered: ‎03-03-2010

Re: Weird "View HDL Instantiation Template" Error

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Thanks for the reply.  I did end up submitting a webcase a while ago.  The problem was solved by updating to ISE 11.5.  I was using ISE 11.1.  Thanks!

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Xilinx Employee
Xilinx Employee
6,300 Views
Registered: ‎08-07-2007

Re: Weird "View HDL Instantiation Template" Error

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This behavior doesn't look correct.  I would make sure your HDL settings all match (it sounds like Verilog?) in your ISE project for prefered language.  I know this works for VHDL and it is possible there is a problem with the Verilog flow.  If you can't resolve this please submit a webcase.

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Newbie moyeretzian
Newbie
6,802 Views
Registered: ‎03-03-2010

Re: Weird "View HDL Instantiation Template" Error

Jump to solution

Thanks for the reply.  I did end up submitting a webcase a while ago.  The problem was solved by updating to ISE 11.5.  I was using ISE 11.1.  Thanks!

View solution in original post

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