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Visitor hyfsysu
Visitor
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Registered: ‎01-16-2019

What algorithm does Xilinx use for division and square-root in the Floating-Point Operator IP?

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I have read the document " Floating-Point Operator v7.1 LogiCORE IP Product Guide ". In Chapter 4 page 33, it says:

"

Cycles per Operation

The Cycles per Operation Vivado IDE parameter describes the minimum number of cycles
that must elapse between inputs. This rate can be specified. A value of 1 allows operands to
be applied on every clock cycle, and results in a fully-parallel circuit. A value greater than 1
enables hardware reuse. The resources consumed by the core reduces as the number of
cycles per operation is increased. A value of 2 approximately halves the resources used. A
fully sequential implementation is obtained when the value is equal to Fraction Width+1 for
the square-root operation, and Fraction Width+2 for the divide operation.

"

I know there are some common algorithms for divison and square-root, such as non-restoring, newton-raphson, goldschmidt, SRT. According to the above description, I guess it uses non-restoring. 

Can anyone give me some information?

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Moderator
Moderator
288 Views
Registered: ‎08-01-2007

回复: What algorithm does Xilinx use for division and square-root in the Floating-Point Operator IP?

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Unfortunately the algorithm info can not shared.

View solution in original post

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Moderator
Moderator
289 Views
Registered: ‎08-01-2007

回复: What algorithm does Xilinx use for division and square-root in the Floating-Point Operator IP?

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Unfortunately the algorithm info can not shared.

View solution in original post

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