02-03-2021 03:23 AM
I am new to FPGA designing, I am using FFT IP core v9.1 in that I was configured target clk 250MHz and 250Msps data throughput. And also I tried with target clk 250Mhz and data throughput 50Msps. I am getting same results in simulation which means clk vs fft output data.
Anyone can explain "What is the difference between 250MHz target clk, 250Msps vs 250MHz target clk, 50Msps". What is the different response get from this two case.
02-03-2021 04:46 AM
Welcome to the Community Forum!
I think you are referring to options seen in the Wizard that helps you setup the FFT core.
As with many Xilinx IP, setting up the IP is a tradeoff between speed and FPGA-resource-usage. For the FFT core, the target clock is used to clock the core. The Msps is the rate at which you want to send data samples to the core.
If you specify a target clock of 250MHz and you specify 250Msps then you are requesting real-time operation of the core. That is, every time you clock a data-sample into the core, you will (after some latency) get a sample out of the core that corresponds to one frequency-bin of the FFT. I think that real-time operation is fastest speed for the core and will use the most resources in the FPGA.
If you specify a target clock of 250MHz and you specify 50Msps then you are operating at less than maximum speed and the core will use fewer resources in the FPGA. For this setup, you will not be sending a data-samples to the core at the target clock rate. This is not a problem. The core will simply wait until it receives enough samples to completely calculate the FFT and then the core will start to output samples of the FFT.
Xilinx document PG109 is your reference for the FFT core. There is lots to read in this well-written document.