I am testing a convolutional encoder verilog code(named 'convolution_v7_0.v) generated from ip core generator.
But it doesn't work as I expected.
I think, the main issue on this is that the value and timing of both ready and output signal are not correct.
In testbench, I just give clock signal, new data, and continuous and constant(1) input for this encoder.
The result waveform captured and attatched in file.
Do you have any suggestion?
Thanks in advance.
Looks like the initial startup/reset/gsr period. I wouldn't worry about it.