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johnjhpark
Newbie
Newbie
2,749 Views
Registered: ‎01-28-2013

What is wrong with this viterbi encoder ip test

Hi.

I am testing a convolutional encoder verilog code(named 'convolution_v7_0.v) generated from ip core generator.

But it doesn't work as I expected.

 

I think, the main issue on this is that the value and timing of both ready and output signal are not correct.

In testbench, I just give clock signal, new data, and continuous and constant(1) input for this encoder.

The result waveform captured and attatched in file.

 

Do you have any suggestion?

Thanks in advance.

 

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test.JPG
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bwiec
Xilinx Employee
Xilinx Employee
2,739 Views
Registered: ‎08-02-2011

Looks like the initial startup/reset/gsr period. I wouldn't worry about it.

www.xilinx.com
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