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arda.shah
Contributor
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Registered: ‎10-31-2012

What's the problem?

Take standart FFT core (FFT8 or 9) and and configure it the following parameters:

1 ch;

1024 tr length;

pipelined arch;

fixed point;

scaled;

conv. round;

12 bit data and 20 width phase factor;

natural order;

non real time.

Further test the core is attached testbench which contain real data from adc and different config_tdata (FFT_TestB.v)

And as a result we get a weird output data:1.jpg

m_axis_data_tdata_re and m_axis_data_tdata_im.

 

What's wrong?

 

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bwiec
Xilinx Employee
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Registered: ‎08-02-2011

Well, looking at the event signals, it appears that tlast is not being driven correctly.
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arda.shah
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2.jpg

in PG109 October 2, 2013, p.51  is no tlast signal

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arda.shah
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3.jpg

 

I do not see a problem with the tlast signal

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muzaffer
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Registered: ‎03-31-2012

The core is telling you that your tlast has a problem (missing & unexpected tlast). Your problem is that tlast should indicate that the current tvalid is the last one, ie it should overlap the tvalid which validates the last valid data. Your tlast has no associated tvalid (so unexpected tlast) and the end of your frame does not have a tlast (missing tlast).

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arda.shah
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I eliminated the error relates to a signal tlast5.jpg

 
but the output data (m_axis_data_tdata_re(im)) is still incorrect
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muzaffer
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Registered: ‎03-31-2012

how do you judge output data to be incorrect? what do you expect, and what do you get? you seem to be reconfiguring the fft every frame. is this really what you want ? also do you give the fft enough time to accept the new configuration?

one test you can try is to give a single pulse to the input of the fft and see if you get the right tone at the output. did you try something simple like that?
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arda.shah
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 I think that the correct data is generated from the demo testbench by the IP core (
taken here and a little changed xfft_1.srcs\sources_1\ip\fft_AXI\demo_tb)
6.jpg
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arda.shah
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I expect the data only on 12 harmonic, like in demo TB.

But get junk at all harmonics

7.jpg

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arda.shah
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, single pulse you mean single frame?

if so then yes, I tried and the result is the same

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arda.shah
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q- you seem to be reconfiguring the fft every frame. is this really what you want ?

a- I just tested in various configurations to see which one is the correct configurations, like in demo testbench.

 

q- also do you give the fft enough time to accept the new configuration?

a- certainly enough time, look at the signal m_axis_data_tvalid.

 

 

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bwiec
Xilinx Employee
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Registered: ‎08-02-2011

I think you need to check the results against matlab. I believe your assumption may be incorrect that you should only see non-zero data values in the two bins. This only happens under very controlled circumstances where coherent sampling condition is satisfied. Since you are taking data off a 'real adc,' changing FFT core parameters, etc, I suspect you are seeing leakage (and/or noise/rounding) effects in the other bins.
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muzaffer
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Registered: ‎03-31-2012

>> single pulse you mean single frame?

No; by single pulse I mean generate input data of all zeros except at one time index (say at N/4) of value 0.5 (half range of the input) and see if you get a sine wave at the output.
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arda.shah
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bwiec, I implemented a software FFT on Zync with the same ADC and I got the expected results.

muzaffer, I will try this case.
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arda.shah
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I don't get a sine wave at the output.
May be problem in range of input data, it's +- 2047 ?
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arda.shah
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Registered: ‎10-31-2012

I think the problem is in the phase shift, as the example described here 

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