cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
368 Views
Registered: ‎11-10-2019

Why Vivado synthesis takes up twice the DSP48 than estimated by HLS sysnthesis

I synthesized and packeged an IP in Vivado HLS and then tried to synthesize it in Vivado with the rest of the logic, but the OOC synthesis reports twice of the DSP48E for that IP. The DSPs were used in HLS only for heavy calculations, while LUTs were used for simple multiply-add operations - which is exactly what I wanted (you can see high LUT utitilization). However, the Vivado synthesis seemed to have shiffted all calculations to be done by DSPs and now it uses minimal amounts of LUTs and a lot of DSPs. Why so?

h_pro.pngv_pro.png  

Tags (2)
0 Kudos
2 Replies
Highlighted
Moderator
Moderator
246 Views
Registered: ‎08-01-2007

are you using Xilinx IP in IP catalog, if you do not, the post should be moved to HLS board.

0 Kudos
Highlighted
Adventurer
Adventurer
216 Views
Registered: ‎11-10-2019

@nathanx ,

I created my own IP in HLS and got the c-synthesis estimated utilization as shown on the screenshot. Then, when this IP is generated via OOC in Vivado, the utilization is very much different. I am not sure to where this issue fits better: is this the HLS problem that underestimates the resources, or this is the Vivado problem that overestimates the resources?

0 Kudos