01-26-2020 01:01 PM - edited 01-26-2020 01:21 PM
I synthesized and packeged an IP in Vivado HLS and then tried to synthesize it in Vivado with the rest of the logic, but the OOC synthesis reports twice of the DSP48E for that IP. The DSPs were used in HLS only for heavy calculations, while LUTs were used for simple multiply-add operations - which is exactly what I wanted (you can see high LUT utitilization). However, the Vivado synthesis seemed to have shiffted all calculations to be done by DSPs and now it uses minimal amounts of LUTs and a lot of DSPs. Why so?
02-09-2020 04:15 PM - edited 02-09-2020 04:15 PM
I created my own IP in HLS and got the c-synthesis estimated utilization as shown on the screenshot. Then, when this IP is generated via OOC in Vivado, the utilization is very much different. I am not sure to where this issue fits better: is this the HLS problem that underestimates the resources, or this is the Vivado problem that overestimates the resources?