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Contributor
Contributor
2,751 Views
Registered: ‎04-14-2009

Why will a design fail in timing with "HDL co-simulation" and pass with the "Bitstream" option ?

Hi,

  

 

 I've two constant multipliers in the design attached. When choosing the "HDL co-simulation" option it fails and I've the following error :

 

  ERROR:Pack:1653 - At least one timing constraint is impossible to meet because

   component delays alone exceed the constraint. A timing constraint summary

   below shows the failing constraints (preceded with an Asterisk (*)). Please

   use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and

   PCF files to identify which constraints and paths are failing because of the

   component delays alone. If the failing path(s) is mapped to Xilinx components

   as expected, consider relaxing the constraint. If it is not mapped to

   components as expected, re-evaluate your HDL and how synthesis is optimizing

   the path. To allow the tools to bypass this error, set the environment

   variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.

 

This error is fixed by changing the latency parameter of both multipliers to '1' instead of the default '0' .

 

However, when choosing the " Bitstream "  option. The design passes.

 

So, why is that ?

 

Note : The design attached is just used to illustrate the point.

 

Thanks,

  Walid F. Abdelfatah 

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