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Observer
Observer
987 Views
Registered: ‎04-08-2019

Working on Pixels (AXI4-Stream) in Model Composer

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Hello,

I'm evaluating Model Composer in comparison to XSG and HLS. For this, I get an AXI4-Stream which transport a bayer-pattern video signal. My IP-Component have to work on the pixel of this stream.

How can I access the diffrent channels of the AXI4-Stream in Model Composer? I need the Data, Clock, tuser and tlast signals. In the UserGuide and the Tutorial I can't find any hints for that.

Thanks and best regards,

Sebastian

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Xilinx Employee
Xilinx Employee
864 Views
Registered: ‎08-11-2017

Thank you for your response and sorry for the delay in getting back to you. 

In Model Composer your designs are represented at a high level of abstraction. If you select AXI4-Stream video as an interface, the generated IP will have side channels for AXI4-stream interface that you expect (like TLAST, TUSER). These side channels do not appear in your high level Model Composer design. In your high level design, you should just focus on processing the pixels of the input image without the need to process the side channels. Model Composer will automatically generate the logic that processes these signals in the generated IP. You need to connect the side channels of the generated IP to proper signals (for example in the IP Integrator tool) for the IP to function correctly.  

As an example, we implemented a demosaicing application in Model composer and generated the IP. At the top-level, the IP looks as shown below which has Data, Clock, TUSER, TLAST ports.

Please let me know if this is not clear or if you have furthur quesitons. 

 

demosicing.pngdemosaicing_IP.png

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Xilinx Employee
Xilinx Employee
946 Views
Registered: ‎05-16-2018

Refer to the XMC UG 1259 (Tutorial). Chapter - 3, page 34. You can see the option Bundle. 

In XMC Userguide refere to the "Interface Block" 

IN general, you can control this from Interface spec block. You can use bundle name in such a way, so that all the signals with same bundle name corresponds to same channel.

Hope this helps. Revert back if this not the one you are expecting and my understanding is different. 

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Observer
Observer
931 Views
Registered: ‎04-08-2019

Thanks for the answer, but unfortunately it does not help me any further.

I want to work on the individual pixel, not the entire picture.
With HLS, I wait for the SOF (tuser) signal and start the processing until the picture is done.

In the settings of the InterfaceSpec I can choose "AXI4-Stream (Video)" with the Video Format Mono, YUV, RGB and N/A.
I have a bayer-pattern video with two green pixel, one red one and one blue one. If I choose the video format "N/A", I get the error "Interface specification for '''' requires video format and video component attributes."

When I select "AXI4-Stream", I can't use the Bundle. The input-form is disabled.

By the way, I'm using Model Composer 2018.3

Best regards, Sebastian

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Xilinx Employee
Xilinx Employee
917 Views
Registered: ‎08-11-2017

Hi Sebastian,

Thank you for your question. I am assuming that each pixel is 8-bit unsigned and you have one AXI4-Stream with 32-bit (4*8) width data going into the IP. Can you please let me know if my assumption is correct?

Thanks

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Observer
Observer
890 Views
Registered: ‎04-08-2019

Hi,

in my application, each pixel is 16-bit unsigned.

Therefore my stream consist of 16-bit tdata plus control signals tlast, tuser, tvalid and tready.

The first line of my video consist of green, blue, green, blue, green, ... pixel
The second line consist of red, green, red, green, red, ... pixel
The third line again: green, blue, green, blue, green, ... pixel
And so on....

When "tuser" signals the beginning of a new frame, I know that the first 16-bit value represents the first green pixel. The next 16-bit value represents the second pixel, which is blue. With the rising edge of tlast I get the end of the line. If I have a resolution of 1280 x 720 pixels, I get after 720 clocks of tlast the last pixel.

Best regards, Sebastian

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Xilinx Employee
Xilinx Employee
865 Views
Registered: ‎08-11-2017

Thank you for your response and sorry for the delay in getting back to you. 

In Model Composer your designs are represented at a high level of abstraction. If you select AXI4-Stream video as an interface, the generated IP will have side channels for AXI4-stream interface that you expect (like TLAST, TUSER). These side channels do not appear in your high level Model Composer design. In your high level design, you should just focus on processing the pixels of the input image without the need to process the side channels. Model Composer will automatically generate the logic that processes these signals in the generated IP. You need to connect the side channels of the generated IP to proper signals (for example in the IP Integrator tool) for the IP to function correctly.  

As an example, we implemented a demosaicing application in Model composer and generated the IP. At the top-level, the IP looks as shown below which has Data, Clock, TUSER, TLAST ports.

Please let me know if this is not clear or if you have furthur quesitons. 

 

demosicing.pngdemosaicing_IP.png

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Observer
Observer
827 Views
Registered: ‎04-08-2019

Thank you for your explanation, now the working method of Model Composer has become clear.

Now I have the problem to separate the color channels of the bayer pattern. I have to manipulate the (high-resolution) image without changing the protocol of the input and the output of my component. But that's another topic.

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Xilinx Employee
Xilinx Employee
797 Views
Registered: ‎05-16-2018

Thanks for confirmation. Please let us know if you need any further help.

Regards

Viswanadh

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