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Visitor
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Registered: ‎01-07-2016

Xilinx FFT core

Hello,

 

I am using the Xilinx FFT core in my design.  I have Four cores working and am trying to expand to use a fifth core.  I am having trouble getting the FDV output to set for one cycle.  What is it that causes the FDV output to go high?  Does anyone have a simulation for the FFT core which shows how this works?  I am trying to develop a simulation for the FFT core using ISIM, but have not been able to get FDV to go high.

 

Thanks.

 

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