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Ramdev9901
Newbie
Newbie
471 Views
Registered: ‎04-03-2020

Xilinx IP Divider Generator 5dot1 NOt able to simulate in my environment : verilog+vhdl mixed simulation

HI

I generated the Divider Generator 5.1 , and i see all the files are generated in vhdl even though i specified the verilog as language .  And i see it is given the "div_gen_0.veo" to integrate in verilog file , which i did, but when i am compiling in vcs it is stuck and complaining below error , need some help 

Parsing design file '../monitor_src/divider/hdl/xbip_utils_v3_0_vh_rfs.vhd'
Info-[SYNTAX-ENCRYPTED] VHDL syntactic or semantic error/warnings detected in the encrypted source
file ../monitor_src/divider/hdl/xbip_utils_v3_0_vh_rfs.vhd. The actual
error message has been suppressed for security reasons. Please contact the
vendor of this file for resolution of this problem

 

Is the generated core can not be simulated in vcs ? 

Is there a way i can generate the verilog file instead of vhdl ?

 

 

Thanks in advance 

 

Regards

Ramdev

 

 

 

 

 

 

 

 

 

 

simulation_settings.PNG
files.PNG
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1 Reply
Ramdev9901
Newbie
Newbie
462 Views
Registered: ‎04-03-2020

Kindly help how to simulate the divide IP core ?
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