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pelgabri
Newbie
Newbie
917 Views
Registered: ‎01-22-2020

Xilinx System Generator with dSpace RTI FPGA Programming Blockset

Hi everyone,

I'm using Matlab/Simulink 2016B with Xilinx Vivado system edition 2017.2 and dSpace release 2017B to configure an FPGA application. 

I'm following the step by step RTIFPGA guide of dSpace, but when the building starts, MATLAB gets stuck at the "Starting synthesis of System Generator output files..."

I created two subsystems, one for the processor model and one for the FPGA model.

SCHEMA.PNG

In the FPGA subsystem I have these blocks, I properly configured the parameters by mean of "FPGA_SETUP_BL1" and I configured the in/out blocks to connect PROCESSOR to FPGA.

SCHEMA_FPGA_INTERNO.PNG

 

The processor subsystem has these elements:

SCHEMA_PROC_INTERNO.PNG

When I try to build the model, Matlab shows me these warning messages and It doesn't continue the process.

Warning.PNGFine.PNG

I really need support about this, I hope someone you knows how to fix this issue...

 

 

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3 Replies
nathanx
Moderator
Moderator
804 Views
Registered: ‎08-01-2007

I guess this is a Matlab warning, can you consul Mathworks for this?

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ravidapu
Xilinx Employee
Xilinx Employee
761 Views
Registered: ‎12-14-2017

Hi,

The issue seems be to be related to path length, make sure you have shorter name of the model, FPGA subsystems and also the working directory. If you avoid the bigger names and directory paths, the issue will probably be go off.

 

Regards,

Raju A.

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rvidal_victor
Newbie
Newbie
396 Views
Registered: ‎03-21-2019

The solution is using a path without blanck spaces.

You would have to move your model from C-Program files, to other route.

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