01-22-2020 06:05 AM
I'm using Matlab/Simulink 2016B with Xilinx Vivado system edition 2017.2 and dSpace release 2017B to configure an FPGA application.
I'm following the step by step RTIFPGA guide of dSpace, but when the building starts, MATLAB gets stuck at the "Starting synthesis of System Generator output files..."
I created two subsystems, one for the processor model and one for the FPGA model.
In the FPGA subsystem I have these blocks, I properly configured the parameters by mean of "FPGA_SETUP_BL1" and I configured the in/out blocks to connect PROCESSOR to FPGA.
The processor subsystem has these elements:
When I try to build the model, Matlab shows me these warning messages and It doesn't continue the process.
I really need support about this, I hope someone you knows how to fix this issue...
02-12-2020 08:11 AM
The issue seems be to be related to path length, make sure you have shorter name of the model, FPGA subsystems and also the working directory. If you avoid the bigger names and directory paths, the issue will probably be go off.