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Visitor
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Registered: ‎08-20-2015

about DDS compiler and parameters

Hi all,

  I am reading some introduction on different 7 series and DDS generator. I am wondering if the DDS compiler is universal to all xilinx series or a each series has it's own DDS compiler to work? I am reading a board Xilinx Zynq-7000 using Artix-7, the board supports up to 4xx MHz clock. But in the document of DDS http://www.xilinx.com/support/documentation/ip_documentation/dds_compiler/v6_0/pg141-dds-compiler.pdf, it is said that the output frequency of the sine wave depends on the system clock frequency, the phase width and the phase increment value. The doc use an example of 120MHz system clock, phase width is 10 and the phase increment value is 12. The output frequency is computed as 1.40MHz.

 

I wonder if the 120MHz refer to the clock input to the DDS module. So the maximum clock is 4xxMHz from the board? If that's true the output frequency is not that high. I am looking for something up to 100MHz.

 

My second question is the DDS doc states that there will be 16 channels of DDS output. Is it possible to compile it so the I synchronize 4 channels in the same clock?

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Hello,

 

There are several things to consider here.

 

When you are looking at the DC and switching datasheet for a given device family (be it zynq, artix, or anything), it lists the delay characteristics for each primitive block based on the device architecture itself. When you actually go to build your logic, you are connecting up many of these blocks in various ways. How you connect these blocks internally and to the outside world can result in a circuit that can max out at hundreds of MHz or maybe only 1MHz (for example).

 

Now when you look at the DDS document, it lists example timing numbers for various devices, speed grades, and IP configurations to help you get some idea of how fast this particular circuit might close timing under optimal conditions (this can still change drastically depending on the rest of the FPGA design.

 

So determining if you can get a 100MHz sine wave out of the DDS is not a simple 'yes' or 'no' answer because it's incomplete specification. DDS makes a tradeoff between frequency and phase resolution. If your 100MHz 'sine wave' only needs 2 samples per period of resolution, then you would need to clock the DDS at 200MHz (to satisfy nyquist) which is doable. However, if you need better resolution than that, then that will continue to push your required clock frequency up.

 

One last thing to consider is that you can do a poly-phase implementation of DDS to run at faster rates. Since the IOs can run faster than general fabric, you can output multiple phases in parallel out of the DDS and then serialize it at the output to get an aggregate output rate that's much faster than what the DDS core itself needs to run at.

 

For example, if your DDS core is running at 100MHz but outputting 4 phases per clock and your serializing that at the IO with an 4:1 rate, then youre sending out 400MSPS.

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Visitor
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Registered: ‎08-20-2015


@bwiec wrote:

Hello,

 

There are several things to consider here.

 

When you are looking at the DC and switching datasheet for a given device family (be it zynq, artix, or anything), it lists the delay characteristics for each primitive block based on the device architecture itself. When you actually go to build your logic, you are connecting up many of these blocks in various ways. How you connect these blocks internally and to the outside world can result in a circuit that can max out at hundreds of MHz or maybe only 1MHz (for example).

 

Now when you look at the DDS document, it lists example timing numbers for various devices, speed grades, and IP configurations to help you get some idea of how fast this particular circuit might close timing under optimal conditions (this can still change drastically depending on the rest of the FPGA design.

 

So determining if you can get a 100MHz sine wave out of the DDS is not a simple 'yes' or 'no' answer because it's incomplete specification. DDS makes a tradeoff between frequency and phase resolution. If your 100MHz 'sine wave' only needs 2 samples per period of resolution, then you would need to clock the DDS at 200MHz (to satisfy nyquist) which is doable. However, if you need better resolution than that, then that will continue to push your required clock frequency up.

 

One last thing to consider is that you can do a poly-phase implementation of DDS to run at faster rates. Since the IOs can run faster than general fabric, you can output multiple phases in parallel out of the DDS and then serialize it at the output to get an aggregate output rate that's much faster than what the DDS core itself needs to run at.

 

For example, if your DDS core is running at 100MHz but outputting 4 phases per clock and your serializing that at the IO with an 4:1 rate, then youre sending out 400MSPS.


Thanks for your reply. That help me to understand a bit more but I still have two questions about the phase resolution and synchronization. I understand what you mean by the tradoff between freq and phase resolution, as well as the dependence of the design with FGPA. But the diriven clock of the DDS is from the main clock of the developement board,  the maximum output frequency limited by the main clock on hte board , is that right?

 

I apology that I didn't put it clear about the phase resolution in my first post. I am going to create two channel of sine wave output. They should be synchronize but one sine have phase offset from the other one. I want to find out how fine the phase difference could be. In the doc http://www.xilinx.com/support/documentation/ip_documentation/dds.pdf, it states that "Optional phase offset capability providing support for multiple synthesizers with precisely controlled phase differences" . It is very vague and  I don'tsee how precise it could be. I am a student and beginner, I have very limited budget on the board so I want to purchase the one that fit my project.

 

As your mean to serialize the parallel output. I am not sure I fully understand that. I am going to output two synchronize channels, each will go to one external amplifier.  but if you serialize  the output, how do we physically separate the outputs?

 

Thanks again for your reply.

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Teacher
Teacher
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Registered: ‎07-09-2009

Yes, DDS output frequency is always going to be lower than the clock frequency.

But you could use the PLL/ DLL if the fpga has one to up the board clock to a faster one.

BTW :
Have a look on web for dds boards,
AD9851 DDS comes to mind,

lots of useful info on the Analog devices web site on DDS chips.
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@drjohnsmith wrote:
Yes, DDS output frequency is always going to be lower than the clock frequency.

But you could use the PLL/ DLL if the fpga has one to up the board clock to a faster one.

BTW :
Have a look on web for dds boards,
AD9851 DDS comes to mind,

lots of useful info on the Analog devices web site on DDS chips.

How do I figure out which one is support PLL?

 

For DDS, do you mean use FGPA to control external DDS chip? I think the same way before but I am focusing on AD9910; however, I just want to know if FGPA  alone be able to do the same job as AD9910, so I can save some money to buy the AD9910. Thanks.

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Teacher
Teacher
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Registered: ‎07-09-2009

How to do ????

   read the data

 

do I mean ???

    no just answering questoins, showing you other DDS chips, and where lot of stuff to read is.

 

Can you do a DDS in an FPGA ?

   yes, how you going to do the DAC.

 

Can you use the PLL / DLL in the FPGA fo a similar job,

   probably.

 

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

But the diriven clock of the DDS is from the main clock of the developement board,  the maximum output frequency limited by the main clock on hte board , is that right?

I think this is what Dr Smith is trying to say. You can take the clock coming from the oscillator on the board to a PLL or MMCM and generate different clock rates from that. So your DDS is not just limited to run at the clock rate of the on-board oscillator. Check out the 'Clocking Wizard' IP.

 

 They should be synchronize but one sine have phase offset from the other one. I want to find out how fine the phase difference could be. In the doc http://www.xilinx.com/support/documentation/ip_documentation/dds.pdf, it states that "Optional phase offset capability providing support for multiple synthesizers with precisely controlled phase differences" . It is very vague and  I don'tsee how precise it could be. I am a student and beginner, I have very limited budget on the board so I want to purchase the one that fit my project.

Okay, just run them on the same clock and they will be 'synchronized' in that you will get a new sample from each at the same clock tick. As you noted, the DDS core allows you to set phase offset. The precision of this value is again dependent on the way you configure the core. Specifically the width of the phase accumulator. There's a delta-theta term in the equations in the datasheet which define your frequency resolution. This is the same value that sets the precision of the phase offset capabilities.

 

As your mean to serialize the parallel output. I am not sure I fully understand that. I am going to output two synchronize channels, each will go to one external amplifier.  but if you serialize  the output, how do we physically separate the outputs?

Sorry, I think the use of the term 'serialize' here is a bit unclear. Take a concrete example. You want a 800MSPS sine wave with 8 bit samples. 800MHz clock is too fast, but 200MHz should work. So you want 4 instances of DDS core @ 200, each one with appropriate phase offset. So now you have 4 parallel 8-bit sine waves at different phase offsets. By 'serialize' in this context means combine those 4 parallel 8-bit paths into one faster 'serial' 8-bit path using OSERDES at the IO. 

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Visitor
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Registered: ‎08-20-2015

Thanks for all your reply. I got some idea now :)

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