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7,307 Views
Registered: ‎01-05-2010

black box interface in system generator

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bonjour :-)

I was facing a problem while simulating an imported HDL module using black box. I am obtaining '0' as a result for every input. I tried importing various different modules such as demux, arithmetic logic unit etc but I am obtaining '0' as a result for all possible cases of inputs.

  While simulating with ModelSim as an external simulator- the modelsim window opens but later an error is reported which reads "error reported by S-function 'sysgen' in '.....Block Box'. A summary of errors has been written to ..._sysgen_error.log."

  The error which has been written into the ..._sysgen_error.log is "error occurred during "Simulation Initialization"."

  The HDL language that I have used is verilog.

  I believe I have fulfilled all the conditions required to import a HDL  module into sysgen that is mentioned in the Sysgen user guide.

  Are there any pre requisites I  need to fulfil to import a HDL module which I have failed to?

  Should I add anything extra to the black box configuration file? 

  Is it a problem with my ise project navigator or the system generator I have installed in my computer?

  If any other mistake, could you please point out the same?

 

 

 

 KINDLY SOLVE MY PROBLEM.......

 

 

 

 

THANK YOU :-)

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5,104 Views
Registered: ‎01-05-2010

hi jim :-)

I finally made the blk box work in sysgen.

I was supposed to declare single bit vectors as [0:0] in verilog :-)

Thanks a lot for your suggestions :-)

 

 

regards,

 

anand.

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blaine
Xilinx Employee
Xilinx Employee
7,295 Views
Registered: ‎04-11-2008

have you got the modelsim token in your MDL?

 

JB

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7,284 Views
Registered: ‎01-05-2010
Yes sir, indeed I have the modelsim token in my MDL and I changed the simulator in my blackbox from none to external and the HDL co-simulator to be used to ModelSim.
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ywu
Xilinx Employee
Xilinx Employee
7,261 Views
Registered: ‎11-28-2007

What error messages are in the _sysgen_error.log?

 

Cheers,
Jim
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7,259 Views
Registered: ‎01-05-2010

The error_log file of the arithmetic logic unit imported to sysgen had the following contents:-

 

 

 

 

Error 0001: Internal Error
     Block: 'alu/Black Box'
--------------------------------------------------------------------------

Error 0001:

Reported by:
  'alu/Black Box'

Details:
An internal error occurred in the Xilinx Blockset Library.

Please report this error to Xilinx (http://support.xilinx.com),
in as much detail as possible. You may also find immediate help
in the Answers Database and other online resources at http://support.xilinx.com.


Error occurred during "Simulation Initialization".

--------------------------------------------------------------------------
 

 

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ywu
Xilinx Employee
Xilinx Employee
7,254 Views
Registered: ‎11-28-2007

I suspect there are some errors in Modelsim. Please take a look at the transcript file from modelsim to see if it has any errors.

 

Cheers,

Jim

 

Cheers,
Jim
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7,231 Views
Registered: ‎01-05-2010

but even when i provide stimulus from the matlab workspace i am getting 0 as the result for every possible cases of input.

is there some critical error which i have not noticed?

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ywu
Xilinx Employee
Xilinx Employee
7,225 Views
Registered: ‎11-28-2007

I take it that you no longer get the "internal error". If that's case, you can add signals to the Modelsim wave window and check if the blackbox indeed gets the stimulus you're providing. It'd help if you can post a snapshot of the waveforms.

 

 


kumar.anand743@gmail.com wrote:

but even when i provide stimulus from the matlab workspace i am getting 0 as the result for every possible cases of input.

is there some critical error which i have not noticed?


 

 

Cheers,
Jim
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7,203 Views
Registered: ‎01-05-2010

 Hi There:-)

The following was the demux design I wrote in verilog and tried to import it to sysgen using black box.

 I tried to sikulate it but obtained 0 as a result for all my inputs. 
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7,201 Views
Registered: ‎01-05-2010
the following was the .mdl file of my blkbox
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4,346 Views
Registered: ‎01-05-2010
the following was the verilog code for the demux i wrote in ISE 9.1.03i and saved it in the directory of my matlab files
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4,347 Views
Registered: ‎01-05-2010
The following was the matlab config file for the blk box
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ywu
Xilinx Employee
Xilinx Employee
4,333 Views
Registered: ‎11-28-2007

I tried it in 11.4 (I don't have 9.1.03 installed any more), the simulation works. However, I did notice a problem with your verilog file. I suggest you simulate just the demux.v in modelsim and check if anything is wrong.  (Hint: your code will infer latches instead of a combinatorial demux).

 


kumar.anand743@gmail.com wrote:
the following was the verilog code for the demux i wrote in ISE 9.1.03i and saved it in the directory of my matlab files

 

 

Cheers,
Jim
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5,105 Views
Registered: ‎01-05-2010

hi jim :-)

I finally made the blk box work in sysgen.

I was supposed to declare single bit vectors as [0:0] in verilog :-)

Thanks a lot for your suggestions :-)

 

 

regards,

 

anand.

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