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Participant
Participant
9,100 Views
Registered: ‎09-21-2007

co-simulation of the blocks in core generator

Hi,
           I want a co-simulation of the MAC unit given in core-generator. I have done with simulation of it using model sim. But I want hardware co-simulation of it. Actually I have tried it with system generator's black box. The box is generated but when I am going for generate in sysgen token it shows me errors, so help me, by any other way I can open Core Generator's block in sysgen?  Can I do the co-simulation? And also how can I integrated two blocks of Core Generator?
I am using ISE 8,2,03, System Generator 8.2 , MATLAB 7.1 (R14), and Spartan-3E starter kit.
Please help me.
 
Thank you, 
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Xilinx Employee
Xilinx Employee
9,088 Views
Registered: ‎08-07-2007

Many cores in CoreGenerator are available as blocks in the System Generator blockset.  There is not a standalone MAC unit but there is a multiplier block as well as an accumulator block that would be easy to use to create a MAC.  Also the FIR Compiler block allows easy creation of a MAC basded FIR filter if that is what you are trying to build. 

If you'd like to bring in a core from CoreGen using the black box interface this is perfectly valid.  There are several black box examples in the System Generator help including one specifically showing how to bring in a Core Generator core:
"Getting Started > Additional Examples and Tutorials > Importing a Xilinx Core Generator Module"

This should help get you started but if you still have further questions please open a case with Xilinx Technical support for help on your specific model here:
http://support.xilinx.com/support/clearexpress/websupport.htm
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Participant
Participant
9,062 Views
Registered: ‎09-21-2007

Thank you,
            I have tried as you say.........It's working on simulation but mostly in VHDL it's not working properly in Verilog, I think black box not support upper letter I/O declaration. I have tried with simple comparator in VHDL and it works. But I want hardware co-simulation with Spartan 3E starter kit and it shows me error :
 
ERROR:NgdBuild:604 - logical block
   'hwcosimtoplevel/sysgen_dut/comp_x0/black_box/BU2' with type
   'comparator_v9_0_c_compare_v9_0_xst_1' could not be resolved. A pin name
   misspelling can cause this, a missing edif or ngc file, or the misspelling of
   a type name. Symbol 'comparator_v9_0_c_compare_v9_0_xst_1' is not supported
   in target 'spartan3e'.
Please help me,
Krunal
 
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Xilinx Employee
Xilinx Employee
9,058 Views
Registered: ‎08-07-2007

The _config.m file created for your HDL black box must be modified to include all files required to synthesize and implement your black box.  In the case of a core this includes the HDL file and any netlist files associated with that core.  The System Generator Black Box help has the details of what lines must be added to include the .ngc or .edn netlist files for synthesis and implementation.


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Participant
Participant
9,050 Views
Registered: ‎09-21-2007

Thank you,
         I have added that .ngc and .edn files in .m file and the co-simulation work properly. Thanks again for your precious answer.
 
Regrds,
Krunal
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