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Contributor
27,059 Views
Registered: ‎06-03-2011

## complex number quantization

Hello,

How a complex number can be quantized in AccelDSP ?

____

Regards

Sofiene

1 Solution

Accepted Solutions
Contributor
27,625 Views
Registered: ‎06-03-2011

Hello Austin,

Thank you for responding,

A classic quantification does.

____

Regards

Sofiene

4 Replies
Scholar
27,057 Views
Registered: ‎02-27-2008

Sofiene,

A complex number has a real part, and an imaginary part.

If you have a communications channel, the real part is typically called the "in-phase" component (I), and the imaginary part is the quadrature (Q) 180 degree component.

For transmitting, one needs to have both I and Q data to modulate the carrier.  For receiving, one is presented with both the I and Q components.

In a fully digital system, there is some resolution of these components:  8 bit, 10 bit, 16 bit, etc. depending on the range of the signals.  The raw channel itself may also be digitized, and may require more bits of resolution, if the entire dynamic range of the received signal needs to be represented.

Typical DSP systems use fixed-point representation, and only as many bits of resolution as are needed (for speed, power, and cost).

Analog to digital (A/D) converters are used to sample the signals, and quantize them (covnert the analog signal into a digital one).

Austin Lesea
Principal Engineer
Xilinx San Jose
Contributor
27,049 Views
Registered: ‎06-03-2011

Hello Austin,

Thank you for responding,

So is it quantized perfectly by the same way of a real number or variable ?

____

Regards

Sofiene

Scholar
27,045 Views
Registered: ‎02-27-2008

Sofiene,

What is a  "real number" or a "variable?"

In reality, there are analog signals (real world).  Those signals are currents, or voltages, varying in time.  Once sampled by an A to D converter, they are now quantitized (sampled, and discretized).  The signals in digital form are whatever the A/D converter was designed to present:  8 bits, 12 bits, 16 bits, even 24 bit converters exist and are used.

These signals are represented by variables in a c program, and are represented by wires and registers in VHDL or verilog.  In a graphical representation tool, like Sysgen for DSP, they are represented by buses, lines, and boxes on the screen.

The samples change on every clock cycle.  The clock gets lost in a c program (abstracted away), but must be considered in verilog or VHDL, as it is critical for a synchronous system.  The clock in this case is the same clock as delivered to the A/D converter.  In a c program, the operations are performed on blocks of data.  In verilog or VHDL (or sysgen) the processing is continuous (never stops).

Austin Lesea
Principal Engineer
Xilinx San Jose
Contributor
27,626 Views
Registered: ‎06-03-2011

Hello Austin,

Thank you for responding,

A classic quantification does.

____

Regards

Sofiene