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Registered: ‎02-25-2019

dds compiler

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i am trying to do PCM/FM   modulation using DDScompiler, for this i feed to it the FTW and form Q and I channels which are fed to the DAC, from the DAC they are fed to a multiplier that transfers to 2.2 GHz frequency, the question is how to get rid of phase distortions of intermediate frequency which formed DDS COMPILER??

20190916_154923.jpg

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Registered: ‎06-21-2017

I think you have a poor clocking structure. 

Does your clock from the DAC come in on a clock capable pin?  Did you optimize the parallel port timing as described in the data sheet for the DAC?  One possible better clock structure.  Run the DDS from the clock out of the clock wizard.  Feed the DDS data into a clock crossing FIFO.  Use the clock coming back from the DAC to read from the FIFO and clock your output reguisters.  Make sure the output registers are I/O registers, not fabric registers.  And you need timing constraints on all of this.

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Registered: ‎06-21-2017

I would suggest adding an ILA at hthe output of the DDS to verify that the distortion is coming from it.  Also how many bits of phase and hoa many bits of output did you comfigure the DDS for?

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Teacher
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Registered: ‎07-09-2009

have you simulated to check you get the expected data out of the DDS ?

If not thats always a great place to start.

Assuming you use the DDS GUI, you should also get a 'picture' of the expected frequency (s)

If your more than 1/5th the cloc frequency out, then the side bands start comming up,  

     for instance if you had a 4 bit DDS counting 0, 3, 6, 9, 12, 15, 2, 5, 8, 11, 14, 1, 4, 7, 10, 13, 0, 3, etc,

      that would give you a better tone than one with a lower clock that counter

   0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 0 , 7 etc...

 

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Screenshot from 2019-09-16 17-22-39.png
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yes, i will get the desired frequency at the output of the dowels, but i can't get rid of the phase distortions
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Registered: ‎06-21-2017

Do you have timing constraints on your design and does the design meet those constraints?

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there is not
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Is this the same DDS that you asked about in https://forums.xilinx.com/t5/Timing-Analysis/Post-Implementation-timing-simulation-error/m-p/957108?  That simulation is showing problems.

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Registered: ‎07-09-2009

Appologies, your right, no picture of the output there,

   I was thinking of me  MatLab verison ...

So your clock is at 320 MHz in the core, are you supplying that correct ?

     what is your output frequency , above 70 Mhz ?

 

 

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no that`s another dds and he output 'clear' sinus and cosinus,but with phase distortions as seen on the spectrum
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my output frequency stable 60 MHz, not more.

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Teacher
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Registered: ‎07-09-2009

that all sounds good then.

To step forward, we need to diagnose is it the DDS , the DAC/ multiplier  setup or the analog filtering.

Have you done the simulation of the DDS ? can you post results please. You should get a nice sine wave in the simulator graphic mode.

have you  checked the clock frequency ?

Get on back to us.

 

 

 

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yes i checked.

 

Screenshot from 2019-09-17 17-10-58.png
Screenshot from 2019-09-17 12-09-45.png
Screenshot from 2019-09-17 12-09-30.png
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i try to use a narrowband FIR filter to get rid of the spurs and smooth the spectrum and it works fine but one channel outputs noise though the filters are the same

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Registered: ‎07-09-2009

If thats meant to be a sine wave, then thats terrible.

with no modulatoin on it , I'd expect a nice clean signal.

 

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Registered: ‎06-21-2017

One of our previous replies indicates that you do not have timing constraints.  You need them and the design needs to meet those constraints.

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but on out dac i have nice clean sin and cos signal .

20190918_093125.jpg
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but in implementation report all timing is pass, and i dont know what need constrained

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Registered: ‎06-21-2017

The sine and cosine don't look all that clean but part of that may be that you are only generating 5.33 samples per cycle.  Still, it looks like there is about a nanosecond of jitter on the signals. 

You need to constrain everything at this frequency.  What FPGA are you using?  Is it an RFSOC with a built in DAC or is it an external DAC?  What does your clocking structure look like?  What is your clock source?  Does it enter your FPGA and go into a clock wizard that initiates a MMCM or PLL?  Vivado needs to know the requency of this clock.  If this is an external DAC, you need constraints on the data to the DAC that tell Vivado the data to clock relationship that the DAC requires.  How is the DAC physically connected to the FPGA?  Is it on teh same board, an FMC expansion card or through some sort of cable?

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a 50mhz clock is fed to the  Artix-7 xc7a200t and goes to the clk_wizard(MMCM), 320mhz out from clk_wizard  which is fed to the DAC clock, from the DAC 320mhz back is fed to the ARTIX which are connected to the DDS COMPILER,and generate data from DDS fed to DAC.

20190918_153038.jpg
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Teacher
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Registered: ‎07-09-2009

Wow, they are big pictures,

Thoise sine and cos waves are terrible,

If you did a FFT on them , you would see multiple harmonics in the waveform,

What filtering do you have on the DAC output ?

Remember your sampling theory,

   You have copies of the fundamental at harmonics of the sample rate,

You need to have a filter on the output of the DAC to get rid of these harmonics,.

http://www.ti.com/lit/an/slaa523a/slaa523a.pdf

If you also think abotu the sine wave your generating,

    you have 5 samples aroud the circle.

            The sine wave is going to be constructed of 5 steps,

    Which agin if you took an ftt of , would have the fundamental you want and lots of "spurs"

https://www.analog.com/media/en/technical-documentation/application-notes/AN-1396.pdf

 

 

 

 

 

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Registered: ‎06-21-2017

I think you have a poor clocking structure. 

Does your clock from the DAC come in on a clock capable pin?  Did you optimize the parallel port timing as described in the data sheet for the DAC?  One possible better clock structure.  Run the DDS from the clock out of the clock wizard.  Feed the DDS data into a clock crossing FIFO.  Use the clock coming back from the DAC to read from the FIFO and clock your output reguisters.  Make sure the output registers are I/O registers, not fabric registers.  And you need timing constraints on all of this.

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