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Visitor
Visitor
10,365 Views
Registered: ‎10-25-2007

digital up converter using VHDL

Help me in programming digital up converter using VHDL.
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3 Replies
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Xilinx Employee
Xilinx Employee
10,348 Views
Registered: ‎08-13-2007

Zihan,
 
Your question (statement) was pretty vague. Are you familiar with DUCs? Are you proficient with VHDL? Do you have specific issues with the implementation processs? Are you have issues with a specific part of the design? Or do you not know where to start?
 
Some additional background here will likely be useful for the users to respond appropriately.
 
I would recommend starting here:
http://www.xilinx.com/bvdocs/appnotes/xapp1018.pdf (Designing Efficient Wireless Digital Up and Down Converters Leveraging CORE Generator and System Generator)
 
Good luck.
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Newbie
Newbie
3,637 Views
Registered: ‎12-19-2013

Hey,

 

I need a up-converter code in VDHL for my research project. Can someone help me?

Captura de pantalla 2013-12-19 a la(s) 18.15.04.png

The interpolator can be split in two parts:

 

Captura de pantalla 2013-12-19 a la(s) 18.15.11.png

 

The LPF must be a FIR filtre of 15 coef. and can be implemented with Matlab tool (<fdatool) 

 

 

The specifications are the next:

- sampling freq. input = 100 Ksps

- BW input = 3kHz

- system clk = 200MHz --> implement a clock system enable for 50Mhz and 100MHz

- DAC samplig freq = 50MHz

- NCO output (sin and cos) = 8 bits

- max NCO freq deviation = 0.5 Hz

- FIR filtre of 15 coef.

 

Thank you in advance

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Xilinx Employee
Xilinx Employee
3,623 Views
Registered: ‎08-01-2008

you can use Xilinx DUC/DDC IPs

http://www.xilinx.com/products/intellectual-property/DUC_DDC_Compiler.htm
Thanks and Regards
Balkrishan
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