digital up converter using VHDL

[zihanzawawi]

Help me in programming digital up converter using VHDL.

[barriet]

Zihan,

Your question (statement) was pretty vague. Are you familiar with DUCs? Are you proficient with VHDL? Do you have specific issues with the implementation processs? Are you have issues with a specific part of the design? Or do you not know where to start?

Some additional background here will likely be useful for the users to respond appropriately.

I would recommend starting here:

http://www.xilinx.com/bvdocs/appnotes/xapp1018.pdf (Designing Efficient Wireless Digital Up and Down Converters Leveraging CORE Generator and System Generator)

Good luck.

[patitofeo]

Hey,

I need a up-converter code in VDHL for my research project. Can someone help me?

The interpolator can be split in two parts:

The LPF must be a FIR filtre of 15 coef. and can be implemented with Matlab tool (<fdatool) 

The specifications are the next:

- sampling freq. input = 100 Ksps

- BW input = 3kHz

- system clk = 200MHz --> implement a clock system enable for 50Mhz and 100MHz

- DAC samplig freq = 50MHz

- NCO output (sin and cos) = 8 bits

- max NCO freq deviation = 0.5 Hz

- FIR filtre of 15 coef.

Thank you in advance

[balkris]

you can use Xilinx DUC/DDC IPs

http://www.xilinx.com/products/intellectual-property/DUC_DDC_Compiler.htm