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Observer batindeko
Observer
2,499 Views
Registered: ‎02-20-2012

divider generator 3.0

Hallo everybody,

I'm using divider generator 3.0  after running the tool shows the following error  Input port 'dividend' is expected to be Fix_27_0, but is Fix_27_11 Error occurred during "Rate and Type Error Checking". I dont know how to configure this block. Another point I use High Radix algorithm. Is somebody know how it works?

Thanks in advance.

camille

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Xilinx Employee
Xilinx Employee
2,494 Views
Registered: ‎08-02-2011

Re: divider generator 3.0

Your divider block is fine, the problem is with the signals driving it. They need to be the correct format according to how you configured the divider. If you simply have a gateway-in or something driving it, simply change its binary point to 11. If something else is driving it, use a reinterpret block before the divider input to force the binary point to 11.

 

I'd also recommend having a look at the getting started guide and some of the labs/examples.

www.xilinx.com
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