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Explorer
Explorer
6,966 Views
Registered: ‎01-30-2011

error in simulation of DDS LOGICORE,

module test;

 

            // Inputs

            reg clk;

            reg we;

            reg [27:0] data;

 

            // Outputs

            wire [5:0] cosine;

            wire [5:0] sine;

 

            // Instantiate the Unit Under Test (UUT)

            dds_compiler_v4_0 uut (

                        .clk(clk),

                        .we(we),

                        .data(data),

                        .cosine(cosine),

                        .sine(sine)

            );

 

 

           

            initial begin

            clk =0;

            forever#10 clk=~clk;

            end

initial begin                   

                        we = 1;

                        data = 60;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                          we = 1;

                        data = 70;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                          we = 1;

                        data = 50;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                          we = 1;

                        data = 80;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                        // Add stimulus here

 

            end

     

endmodule

 

ERROR:HDLCompiler:559 - "C:/Documents and Settings/Administrator/Desktop/test.v" Line 37: Could not find module/primitive <dds_compiler_v4_0>.

 

sir , in the bold line error is coming.

 

this is a simulated code.i got the implementation code through dds logicore. but i can't get the output waveform.

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Xilinx Employee
Xilinx Employee
6,964 Views
Registered: ‎11-28-2007

Re: error in simulation of DDS LOGICORE,

Are you running simulation from Project Navigator?

Cheers,
Jim
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Explorer
Explorer
6,960 Views
Registered: ‎01-30-2011

Re: error in simulation of DDS LOGICORE,

yah i am running simulation from Project Navigator.if this is not the right method,then specify the correct methd sir. thank u

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Xilinx Employee
Xilinx Employee
6,952 Views
Registered: ‎11-28-2007

Re: error in simulation of DDS LOGICORE,

Nothing wrong with roject Navigator. Just needed to know your design flow so I can ask more questions ;). Can you attach a snapshot of the "Design" window similar to the one below so I can see the simulation file hierarchy and how the DDS core is brought into the project?

 

ScreenHunter_20.jpg

 


@technovlsi wrote:

yah i am running simulation from Project Navigator.if this is not the right method,then specify the correct methd sir. thank u




Cheers,
Jim
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Explorer
6,946 Views
Registered: ‎01-30-2011

Re: error in simulation of DDS LOGICORE,


@jimwu wrote:

Nothing wrong with roject Navigator. Just needed to know your design flow so I can ask more questions ;). Can you attach a snapshot of the "Design" window similar to the one below so I can see the simulation file hierarchy and how the DDS core is brought into the project?

 

ScreenHunter_20.jpg

 


sir,i am telling the process which i now folloed is :

1> create a new project

2 > go to new source and select logicore >give the name and then finish

3>logicore window generate,from there i go to dsp blocks,select DDS from wave synthesis

4>specify the required parameter,and then generate.

5> in main prject nevigator, dds core is generated (as per pic u give)

6> go the file,select open,take dds.vho file.

7>create a new .vhd file and add component from thar .vhvo file.

8> synthesis,result is ok.

9>create vhdl testbench. that is also,ok.(not shown the previous error)

10.now in isim simulation i get the null value whatever value i give in data_in.

plz help.:womansad:


 

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Xilinx Employee
Xilinx Employee
6,944 Views
Registered: ‎11-28-2007

Re: error in simulation of DDS LOGICORE,

Good to see that you got past the error in your first post. Can you attach a snapshot of the waveform with all the signals that  shows the problem?

 


@technovlsi wrote:

sir,i am telling the process which i now folloed is :

1> create a new project

2 > go to new source and select logicore >give the name and then finish

3>logicore window generate,from there i go to dsp blocks,select DDS from wave synthesis

4>specify the required parameter,and then generate.

5> in main prject nevigator, dds core is generated (as per pic u give)

6> go the file,select open,take dds.vho file.

7>create a new .vhd file and add component from thar .vhvo file.

8> synthesis,result is ok.

9>create vhdl testbench. that is also,ok.(not shown the previous error)

10.now in isim simulation i get the null value whatever value i give in data_in.

plz help.:womansad:


 




Cheers,
Jim
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Explorer
Explorer
6,941 Views
Registered: ‎01-30-2011

Re: error in simulation of DDS LOGICORE,


@jimwu wrote:

Good to see that you got past the error in your first post. Can you attach a snapshot of the waveform with all the signals that  shows the problem?

 


sir,i attach the neccessary documents.there i got the waveform through isim when i run in verilog textfixture. plz check  the output wave (in attachment). i have also attach the testbench code whwre t got error. plz help.

 


 

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Explorer
Explorer
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Registered: ‎01-30-2011

Re: error in simulation of DDS LOGICORE,

 sir, i use this dds core to produce sine,cosine values only which will be worked as a lut in my hanning window program [suggession got from one of xilinx guy].so i use wave synthesis dds core. am i correct sir???

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Xilinx Employee
Xilinx Employee
6,936 Views
Registered: ‎11-28-2007

Re: error in simulation of DDS LOGICORE,

Are you already working with the Techinical support (webcase) or an FAE on this? If yes, please continue working with them so we are not duplicating effort on the support side.

 


@technovlsi wrote:

 sir, i use this dds core to produce sine,cosine values only which will be worked as a lut in my hanning window program [suggession got from one of xilinx guy].so i use wave synthesis dds core. am i correct sir???




Cheers,
Jim
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Explorer
Explorer
6,934 Views
Registered: ‎01-30-2011

Re: error in simulation of DDS LOGICORE,


@jimwu wrote:

Are you already working with the Techinical support (webcase) or an FAE on this? If yes, please continue working with them so we are not duplicating effort on the support side.

 


no sir,  i am not working with any technical support,nor i hav'nt any fae on this. in the general discussion,a xilinx biggener suggest me to use dds core for sin/cosine values. u need not to duplicate effort sir.moreover i ,first time get instance responce from an expart like u sir. so plz help me. its urjent for my design.




 

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Explorer
Explorer
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Registered: ‎01-30-2011

Re: error in simulation of DDS LOGICORE,

@ jimwu

 

plz see the link

http://xlnx.lithium.com/t5/Digital-Signal-Processing-IP-and/vhdl-code-for-hamming-window/m-p/156828

 

here u adviced me to use DDS core. now lz resolved my problem sir. its very urjent.

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Xilinx Employee
Xilinx Employee
3,713 Views
Registered: ‎08-02-2011

Re: error in simulation of DDS LOGICORE,

Hey, this looks familiar (saw this on edaboard).

 

See this link regarding your error:

AR #32975 - 11.2 XST - " ERROR:HDLCompiler:410 - "<file>.vhd" Line xx: Expression has x elements; expected y"

 

Also, how do you know your waveform is wrong? You can only even see one clock cycle. I suspect if you run your sim longer and zoom out, you will see more like what you are looking for.

 

Unless I am missing something.

www.xilinx.com
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Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

Re: error in simulation of DDS LOGICORE,

First of all, I suggest you read through the DDS core dataqsheet ( http://www.xilinx.com/support/documentation/ip_documentation/ds794_dds_compiler.pdf ) to understand how it works. (by the way, download Xilinx Document Navigator to manage all HW/SW docs)

 

Several things:

* you don't need to set data_in to get outputs from the DDS core

* you can't generate a 100MHz sin/cos signals with a 100MHz system clock (thinking Nyquist frequency)

* when you post your waveform, make sure it's zoomed out a lillte bit so it shows clock transitiions. For DDS especially, if your output frequency is low, you will need to run simulation for a long time before you see output change.

 

 

 


@technovlsi wrote:

@jimwu wrote:

Good to see that you got past the error in your first post. Can you attach a snapshot of the waveform with all the signals that  shows the problem?

 


sir,i attach the neccessary documents.there i got the waveform through isim when i run in verilog textfixture. plz check  the output wave (in attachment). i have also attach the testbench code whwre t got error. plz help.

 


 




Cheers,
Jim
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