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ram@119
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Registered: ‎12-18-2018

errors due to simulation generation,black box unable for inherit sample time from system generator

Hi

 I am implementing  verilog code into simulink using system generator, I am using HDL Netlist compilation and using vivado simulator in black box. I keep getting errors like


The S-function 'sysgen' in 'addii/Constant' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED.

please respond kindly  

Screenshot (74).png
Screenshot (75).png
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meherp
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Registered: ‎08-16-2018

ram@119

 

Note that 'gateway in' block is used for 'simulink block'. 

But you are using 'xilinx's constant block' therefore 'gateway in' is not required. 

Remove the 'gateway in' block and design will work fine. 


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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ram@119
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Registered: ‎12-18-2018

I had remove the 'gateway in' in the design but still getting errors like:
The S-function 'sysgen' in 'plusss/Gateway Out' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED.can you please send me a simple example about black box so that it will help to complete my project and please respond kindly
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G7
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Registered: ‎09-24-2020

Hi

How did you resolve this error

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