errors due to simulation generation,black box unable for inherit sample time from system generator

[ram@119]

Hi

 I am implementing  verilog code into simulink using system generator, I am using HDL Netlist compilation and using vivado simulator in black box. I keep getting errors like

The S-function 'sysgen' in 'addii/Constant' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED.

please respond kindly  

[meherp]

ram@119

Note that 'gateway in' block is used for 'simulink block'. 

But you are using 'xilinx's constant block' therefore 'gateway in' is not required. 

Remove the 'gateway in' block and design will work fine. 

[ram@119]

I had remove the 'gateway in' in the design but still getting errors like:
The S-function 'sysgen' in 'plusss/Gateway Out' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED.can you please send me a simple example about black box so that it will help to complete my project and please respond kindly

[G7]

Hi

How did you resolve this error