12-18-2018 10:20 PM - edited 12-19-2018 07:07 PM
I am implementing verilog code into simulink using system generator, I am using HDL Netlist compilation and using vivado simulator in black box. I keep getting errors like
The S-function 'sysgen' in 'addii/Constant' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED.
please respond kindly
01-13-2019 04:38 AM
Note that 'gateway in' block is used for 'simulink block'.
But you are using 'xilinx's constant block' therefore 'gateway in' is not required.
Remove the 'gateway in' block and design will work fine.
02-13-2019 08:52 PM