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Visitor abhinay9940
Visitor
7,906 Views
Registered: ‎01-28-2016

fft core v7.1 inverse fft not working

Hi,

     I'm trying to simulate the xilinx fft core v7.1 with 1024 point input, radix-4 burst I/O architecture. Even though the signal fwd_inv is zero, the core is performing forward fft. The following is the ISIM screenshot:ifft_not_working.PNGI've read in the datasheet that sclr resets the core to perform forward fft. I suspected that the timing as shown in above picture is incorrect (setting fwd_inv_we to '1' in the immediate clock cycle following sclr being set to '1'), so I've set both start and fwd_inv_we to '1' after one clock cycle following sclr being set to '1'. In this case, rfd never goes high. Only when start is set in the immediate clock cycle following sclr set to '1' does rfd go high. I've omitted sclr by regenerating the core and observed that rfd never goes high even though start was set to '1' for one clock cycle. The following is the screenshot:

no_rfd.PNG

The following is the testbench code for both the simulations:

Simulation 1:

-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  use IEEE.std_logic_arith.all;
  --USE ieee.numeric_std.ALL;
  use std.textio.all;
  use ieee.std_logic_textio.all;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS 
        signal clk : STD_LOGIC := 'X'; 
	signal ce : STD_LOGIC := 'X'; 
	signal sclr : STD_LOGIC := 'X'; 
	signal start : STD_LOGIC := 'X'; 
	signal unload : STD_LOGIC := 'X'; 
	signal fwd_inv : STD_LOGIC := 'X'; 
	signal fwd_inv_we : STD_LOGIC := 'X'; 
	signal rfd : STD_LOGIC; 
	signal busy : STD_LOGIC; 
	signal edone : STD_LOGIC; 
	signal done : STD_LOGIC; 
	signal dv : STD_LOGIC; 
	signal xn_re : STD_LOGIC_VECTOR ( 33 downto 0 ); 
	signal xn_im : STD_LOGIC_VECTOR ( 33 downto 0 ); 
	signal xn_index : STD_LOGIC_VECTOR ( 9 downto 0 ); 
	signal xk_index : STD_LOGIC_VECTOR ( 9 downto 0 ); 
	signal xk_re : STD_LOGIC_VECTOR ( 44 downto 0 ); 
	signal xk_im : STD_LOGIC_VECTOR ( 44 downto 0 );

  BEGIN

  -- Component Instantiation
          uut: entity work.xfft_v7_1 PORT MAP(
                clk => clk, 
		ce  => ce,
		sclr => sclr,
		start => start, 
		unload => unload,
		fwd_inv => fwd_inv,
		fwd_inv_we => fwd_inv_we,
		rfd => rfd,
		busy => busy,
		edone => edone,
		done => done,
		dv => dv,
		xn_re => xn_re,
		xn_im => xn_im,
		xn_index => xn_index, 
		xk_index => xk_index,
		xk_re => xk_re,
		xk_im => xk_im
          );


--  --  Test Bench Statements
--     tb : PROCESS
--     BEGIN
--
--        wait for 100 ns; -- wait until global set/reset completes
--
--        -- Add user defined stimulus here
--
--        wait; -- will wait forever
--     END PROCESS tb;
--  --  End Test Bench 
		clk_process :process
			begin
				clk <= '1';
				wait for 5 us;
				clk <= '0';
				wait for 5 us;
			end process;
			
		stim_proc: process
			variable real_l, imag_l: line;
			file real_file: text is in "real_fp_bin.txt";
			file imag_file: text is in "float_fp_bin.txt";
			variable xn_re_var, xn_im_var: STD_LOGIC_VECTOR ( 33 downto 0 );
			file fp1, fp2: text;
			variable my_line_real, my_line_imag: line;
		begin
			wait for 10 us;
			ce <= '1';
			sclr <= '1';
			wait for 10 us;
			sclr <= '0';
			fwd_inv <= '0';
			fwd_inv_we <= '1';
			start <= '1';
			wait for 10 us;
			fwd_inv_we <= '0';
			start <= '0';	
			wait until rfd'event and rfd='1';
				readline(real_file, real_l);
				readline(imag_file, imag_l);
				read(real_l, xn_re_var);
				read(imag_l, xn_im_var);
				xn_re <= xn_re_var;
				xn_im <= xn_im_var;
			for i in 1 to 1023 loop
				wait for 10 us;
				readline(real_file, real_l);
				readline(imag_file, imag_l);
				read(real_l, xn_re_var);
				read(imag_l, xn_im_var);
				xn_re <= xn_re_var;
				xn_im <= xn_im_var;
			end loop;
			wait until dv'event and dv='1';
				FILE_OPEN (fp1, "inv_real.txt", WRITE_MODE);
				FILE_OPEN (fp2, "inv_imag.txt", WRITE_MODE);
				write(my_line_real, xk_re);
				writeline(fp1, my_line_real);
				write(my_line_imag, xk_im);
				writeline(fp2, my_line_imag);
			for i in 1 to 1023 loop
				wait for 10 us;
				write(my_line_real, xk_re);
				writeline(fp1, my_line_real);
				write(my_line_imag, xk_im);
				writeline(fp2, my_line_imag);
			end loop;
			file_close(fp1);
			file_close(fp2);
			wait;
		end process;		
		unload <= edone;
		
		
end;

Simulation 2:

-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  use IEEE.std_logic_arith.all;
  --USE ieee.numeric_std.ALL;
  use std.textio.all;
  use ieee.std_logic_textio.all;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS 

  -- Component Declaration
--          COMPONENT <component name>
--          PORT(
--                  <port1> : IN std_logic;
--                  <port2> : IN std_logic_vector(3 downto 0);       
--                  <port3> : OUT std_logic_vector(3 downto 0)
--                  );
--          END COMPONENT;

        signal clk : STD_LOGIC := 'X'; 
	-- signal ce : STD_LOGIC := 'X'; 
	--signal sclr : STD_LOGIC := 'X'; 
	signal start : STD_LOGIC := 'X'; 
	signal unload : STD_LOGIC := 'X'; 
	signal fwd_inv : STD_LOGIC := 'X'; 
	signal fwd_inv_we : STD_LOGIC := 'X'; 
	signal rfd : STD_LOGIC; 
	signal busy : STD_LOGIC; 
	signal edone : STD_LOGIC; 
	signal done : STD_LOGIC; 
	signal dv : STD_LOGIC; 
	signal xn_re : STD_LOGIC_VECTOR ( 33 downto 0 ); 
	signal xn_im : STD_LOGIC_VECTOR ( 33 downto 0 ); 
	signal xn_index : STD_LOGIC_VECTOR ( 9 downto 0 ); 
	signal xk_index : STD_LOGIC_VECTOR ( 9 downto 0 ); 
	signal xk_re : STD_LOGIC_VECTOR ( 44 downto 0 ); 
	signal xk_im : STD_LOGIC_VECTOR ( 44 downto 0 );
          

  BEGIN

  -- Component Instantiation
          uut: entity work.xfft2_v7_1 PORT MAP(
                clk => clk, 
		--ce  => ce,
		--sclr => sclr,
		start => start, 
		unload => unload,
		fwd_inv => fwd_inv,
		fwd_inv_we => fwd_inv_we,
		rfd => rfd,
		busy => busy,
		edone => edone,
		done => done,
		dv => dv,
		xn_re => xn_re,
		xn_im => xn_im,
		xn_index => xn_index, 
		xk_index => xk_index,
		xk_re => xk_re,
		xk_im => xk_im
          );


--  --  Test Bench Statements
--     tb : PROCESS
--     BEGIN
--
--        wait for 100 ns; -- wait until global set/reset completes
--
--        -- Add user defined stimulus here
--
--        wait; -- will wait forever
--     END PROCESS tb;
--  --  End Test Bench 
		clk_process :process
			begin
				clk <= '1';
				wait for 5 us;
				clk <= '0';
				wait for 5 us;
			end process;
			
		stim_proc: process
			variable real_l, imag_l: line;
			file real_file: text is in "real_fp_bin.txt";
			file imag_file: text is in "float_fp_bin.txt";
			variable xn_re_var, xn_im_var: STD_LOGIC_VECTOR ( 33 downto 0 );
			file fp1, fp2: text;
			variable my_line_real, my_line_imag: line;
		begin			
			wait for 10 us;
			fwd_inv_we <= '1';
			fwd_inv <= '0';
			start <= '1';
			wait for 10 us;			
			fwd_inv_we <= '0';
			start <= '0';			
			wait until rfd'event and rfd='1';
				readline(real_file, real_l);
				readline(imag_file, imag_l);
				read(real_l, xn_re_var);
				read(imag_l, xn_im_var);
				xn_re <= xn_re_var;
				xn_im <= xn_im_var;
			for i in 1 to 1023 loop
				wait for 10 us;
				readline(real_file, real_l);
				readline(imag_file, imag_l);
				read(real_l, xn_re_var);
				read(imag_l, xn_im_var);
				xn_re <= xn_re_var;
				xn_im <= xn_im_var;
			end loop;
			wait until dv'event and dv='1';
				FILE_OPEN (fp1, "inv_real2.txt", WRITE_MODE);
				FILE_OPEN (fp2, "inv_imag2.txt", WRITE_MODE);
				write(my_line_real, xk_re);
				writeline(fp1, my_line_real);
				write(my_line_imag, xk_im);
				writeline(fp2, my_line_imag);
			for i in 1 to 1023 loop
				wait for 10 us;
				write(my_line_real, xk_re);
				writeline(fp1, my_line_real);
				write(my_line_imag, xk_im);
				writeline(fp2, my_line_imag);
			end loop;
			file_close(fp1);
			file_close(fp2);
			wait;
		end process;		
		unload <= edone;		
end;
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