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giulio.gabelli
Observer
Observer
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Registered: ‎05-23-2014

fir compiler issue generated from encrypted envelop

I have an issue with a FIR compiler IP working with Vivado 2018.1

I am trying to instantiate two Fir Compiler IPs into a SystemVerilog module (will call them fir_1 and fir_2; IP settings are written in the dl_ip.tcl file attached)

We need to instantiate fir_2 within a generate-for loop and fir_1 outside the same loop.

  • in the example design attached I instantiate 
    • fir_1 outside the loop
    • fir_2_in_loop : instance of fir_2 placed inside the generate for loop
    • fir_2_out_loop : instance of fir_2 placed outside the generate for loop
  • fir_ips.tcl can be sourced to generate the two IPs

With these two IPs we have the following behavior:

  • with "Global" output products we have the following Errors:
    • ERROR: [Synth 8-5809] Error generated from encrypted envelope. ..... /hdl/fir_compiler_v7_2_vh_rfs.vhd:61266]
      ERROR: [Synth 8-285] failed synthesizing module 'fir_2' [ .... fir_2/synth/fir_2.vhd:73]
  • if we comment fir_2_out_loop the error is still present
  • if we comment fir_2_in_loop the error disappears

How to get rid of this Error:

  • if we comment fir_2_in_loop the error disappears
    • naturally this is not a posible solution since we need it in the generate-for loop
  • if we leave the fir_2_in_loop instance (comment both fr_1 and fir_2_out_loop) synthesis is completed
    • this is not a solution since we need fir_1 as well
  • using "out of context" output products for fir_2 synthesis is complete
    • this solution can work temporarly, but we wonder why this error is risen

Also, I wonder if this error is solved in other Vivado versions.

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nathanx
Moderator
Moderator
364 Views
Registered: ‎08-01-2007

The error "ERROR: [Synth 8-5809] Error generated from encrypted envelope. ..... /hdl/fir_compiler_v7_2_vh_rfs.vhd:61266]" indicates synthesis tool could not find the source code of the IP.

Can you try Out-of-Context Flow in UG896 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug896-vivado-ip.pdf?

The generate for loop is not a supported flow to instantiate IP, take a look at UG986 for more info.

 

 

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