11-02-2020 12:22 AM
I have an issue with a FIR compiler IP working with Vivado 2018.1
I am trying to instantiate two Fir Compiler IPs into a SystemVerilog module (will call them fir_1 and fir_2; IP settings are written in the dl_ip.tcl file attached)
We need to instantiate fir_2 within a generate-for loop and fir_1 outside the same loop.
With these two IPs we have the following behavior:
How to get rid of this Error:
Also, I wonder if this error is solved in other Vivado versions.
11-24-2020 12:54 AM
The error "ERROR: [Synth 8-5809] Error generated from encrypted envelope. ..... /hdl/fir_compiler_v7_2_vh_rfs.vhd:61266]" indicates synthesis tool could not find the source code of the IP.
Can you try Out-of-Context Flow in UG896 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug896-vivado-ip.pdf?
The generate for loop is not a supported flow to instantiate IP, take a look at UG986 for more info.