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531 Views
Registered: ‎02-07-2019

floating point IP logicore: accumulator

How to use floating point accumulator ip core

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Moderator
Moderator
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Registered: ‎05-02-2017

Re: floating point IP logicore: accumulator

 

hi @creationrgukt123 ,

 

Floating Point only generate the demo_tb testbench which you can add in your project which can help you to simulate the core. Example design for this core is not available so you can't generate it . 

In the product there are some example on this core which can help you to create your own testbench . 

https://www.xilinx.com/support/documentation/ip_documentation/floating_point/v7_0/pg060-floating-point.pdf

The demo testbench only available for VHDL user as product guide mentioned

Regards
Chandra sekhar
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491 Views
Registered: ‎02-07-2019

Re: floating point IP logicore: accumulator

sir actually i want to add an array of floating point values and store it in single register using floating point accumulator. But i am unable to understand some terms like t_last signal .
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-18-2018

Re: floating point IP logicore: accumulator

Hi @creationrgukt123 

The Tlast signal, Tvalid and Tready signals are part of the AXI-Streaming protocol. Please refer to the UG761 and the references provided in it to understand more about the use of AXI-Stream protocol.

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