03-28-2019 10:04 AM
hi @creationrgukt123 ,
Floating Point only generate the demo_tb testbench which you can add in your project which can help you to simulate the core. Example design for this core is not available so you can't generate it .
In the product there are some example on this core which can help you to create your own testbench .
The demo testbench only available for VHDL user as product guide mentioned
03-29-2019 12:18 AM
04-24-2019 10:10 PM
The Tlast signal, Tvalid and Tready signals are part of the AXI-Streaming protocol. Please refer to the UG761 and the references provided in it to understand more about the use of AXI-Stream protocol.