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Visitor
7,046 Views
Registered: ‎07-28-2011

## floating point division using ip cores.

Hi,

I am sriharsha.S

I am using IP coresfor division.

I want to use floating point divider.

I used a 32 bit A, B.

i am using 28 bits for exponent and 4 bits for fractional part.

The RESULT=A/B.

i used A = 30000

B=180

But, i am not getting the answer correctly.

Can any one help me???/

1 Solution

Accepted Solutions
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Xilinx Employee
7,893 Views
Registered: ‎11-28-2007

## Re: floating point division using ip cores.

A couple of things are mixed up here:

The floating point core works with floating point numbers, which is an IEEE standard ( http://en.wikipedia.org/wiki/Floating_point ). You need to convert your inputs to that format and convert the output back to a human readable decimal.

@santhapurharsha wrote:

Hi ,

i am using Xilinx divider core 3.0,

It is a divider.

Open FLOATING point CORE,

and there, u will find many operations, in which divider is an opertation.

I used that core.

i will attach a data sheet/ pdf even about that core.

Cheers,
Jim
8 Replies
Highlighted
7,040 Views
Registered: ‎10-05-2010

## Re: floating point division using ip cores.

What's the answer you're getting? What were you expecting?

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Visitor
7,029 Views
Registered: ‎07-28-2011

## Re: floating point division using ip cores.

Hi,

I am using 16 bit exponent width , 4 bit fractional width.

I am attaching  my code and test bench.

I am using version 13.1.

i will also attach the rsult.

I have given input as a=18000, b= 230.

Bu t wat all i got the result is not wat we expect.

/////////////////////////////////////////////////////////////////////////////////////////////////////

code

////////////////////////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module divflt1(input clk,

input [19:0] div,

input cen,

input  [19:0] den,

output   flow,

output redy,

output  [19:0] out
);

fltcore uut (.a(div),

.b(den),

.clk(clk),

.ce(cen),

.result(out),

.overflow(flow),

.rdy(redy));

endmodule

////////////////////////////////////////

test bench

///////////////////////////////////////

`timescale 1ns / 1ps

module divflt2;

// Inputs

reg clk;

reg [19:0] div;

reg cen;

reg [19:0] den;

// Outputs

wire flow;

wire redy;

wire [19:0] out;

// Instantiate the Unit Under Test (UUT)

divflt1 uut (.clk(clk),

.div(div), .cen(cen),

.den(den),

.flow(flow),

.redy(redy),

.out(out));

initial begin    // Initialize Inputs

clk = 0;

div = 0;

cen = 0;

den = 0;

// Wait 100 ns for global reset to finish

#100  clk=1;

cen=1;

div=18000;

den= 230;

end

always begin

#5 clk=~clk;

end

endmodule

////////////////////////////////////////
The result image is attached...

Highlighted
7,024 Views
Registered: ‎10-05-2010

## Re: floating point division using ip cores.

Which core are you using? It doesn't look like the Xilinx divider core 3.0, since that has two outputs (quotient and fractional), or 4.0 (AXI4 interface).

Please give us *all* of the information we need to investigate your problem.

Highlighted
Visitor
7,021 Views
Registered: ‎07-28-2011

## Re: floating point division using ip cores.

Hi ,

i am using Xilinx divider core 3.0,

It is a divider.

Open FLOATING point CORE,

and there, u will find many operations, in which divider is an opertation.

I used that core.

i will attach a data sheet/ pdf even about that core.

Highlighted
Visitor
7,020 Views
Registered: ‎07-28-2011

## Re: floating point division using ip cores.

Hi,

Please use the code and testbench that  i have provoded and run the simulation.

U wil get the same result as i have shown in the attachment earlier.

Use the floating point divider core only.

Dont use the general divider core.

The general core  divider have two outputs, where as the floating point divider have only one output. PLEASE  find that also..

Thanks...

Highlighted
7,014 Views
Registered: ‎10-05-2010

## Re: floating point division using ip cores.

The floating point divider core uses floating point inputs. You still have not stated what the result you're expecting is. If you're expecting an answer of 30000/180 = 166.67, then your inputs are wrong. Your test bench assigns them as if they were integers, but they are actually floating point numbers following your 16+4 scheme.

I'm not confident I've converted it properly, but integer 30000 corresponds to 2^-7 + 2^-8 + 2^-9 + 2^-10 + 2^-12 + 2^-15 + 2^-16 = .01493835449218750000

180 is .00785541534423828125

Divide these two, and I get 0.24863421148476387034

Converting your UUT's output to floating point and I get.. 1.90166322690299866456.

Well, my sums may be completely wrong here, and I'm in a hurry to knock off for the weekend, but hopefully you get the idea of what the problem is.

If you think I've misinterpreted the problem, please tell us exactly what output you're expecting, and why.

Highlighted
Xilinx Employee
7,894 Views
Registered: ‎11-28-2007

## Re: floating point division using ip cores.

A couple of things are mixed up here:

The floating point core works with floating point numbers, which is an IEEE standard ( http://en.wikipedia.org/wiki/Floating_point ). You need to convert your inputs to that format and convert the output back to a human readable decimal.

@santhapurharsha wrote:

Hi ,

i am using Xilinx divider core 3.0,

It is a divider.

Open FLOATING point CORE,

and there, u will find many operations, in which divider is an opertation.

I used that core.

i will attach a data sheet/ pdf even about that core.

Cheers,
Jim
Highlighted
Visitor
6,994 Views
Registered: ‎07-28-2011