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anee_anil
Adventurer
Adventurer
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Registered: ‎01-16-2008

how to design FIR filter withh fpga

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hi all,

how to create a FIR filter using sysgen with all filter specifications.

fs=?

clock period = ?

clock freuency=?

f1=?

f2 =?

and how to create top level .vhd for that desig?

please explain. i am waiting for your reply.

thanks in advance.

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anee_anil
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Registered: ‎01-16-2008
Thanks sandeep It works good. thanks for your suggestion.

View solution in original post

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benchan
Explorer
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Registered: ‎09-28-2007

Not sure it's comprehensive enough, but you may take a look of the "Designing Filters" chapter in the System Generator Getting Started guide. Also, FIR compiler section in the SysGen block set user guide can be useful.

 

http://www.xilinx.com/support/sw_manuals/sysgen_gs.pdf

 

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anee_anil
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Registered: ‎01-16-2008
Thanks benchan, here i am giving inputs as 2 added sine wave and i am low pass filtering that using fir compiler_v3.1. Through core generator i added fir compiler as black box to my design. I hope i did mistake while generating fir compiler through coregen. My inputs are Fs = 250mhz f1= 7.815mhz f2 = 31.25mhz fda block parameters are low pass fir filter order = 30 Wpass = 1 Wstop = 1000. please help me to generate fir compiler from core gen for my specific design. i have attached my design.As i reffered this from avnet materials. please mention whether to create top level from hand or sysgen will create for us to our design. thanks in advance
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balkris
Xilinx Employee
Xilinx Employee
33,344 Views
Registered: ‎08-01-2008

 

 

Use matlab tool fdatool for filter design

 

matlab workspace >fdatool

 

export coffcient  for system generator FIR block

 

For implementing FIR filter in system Generator u need use Gatway in , FIR block, Gatway out blocks

 

Let me know if u unable to do

 

Regards

Balkrishan 

Xilinx India

Thanks and Regards
Balkrishan
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anee_anil
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Registered: ‎01-16-2008
Thanks Balkrishan , my design worked perfectly before adding blackbox to the design. after adding blackbox, following errors occured 1. Rates and types converged for the feedback path through these blocks. However, the solution contains unknowns. Could not establish rates for the blocks listed at the end of this message. You may need to add an "Assert" block to instruct the system how to resolve rates and types. 2. In the debugging of this problem, you may find it helpful to have the sample rates displayed on the Simulink diagram. This will happen if you open the System Generator block's dialog box, set its "Block Icon Display" control to "Sample Rates", and then update the diagram. Error reported by S-function 'sdsprebuff2' in 'sp3_FIR/Spectrum Scope/Optional Buffering/Buffer': Continuous sample times are not allowed. 3. Block initialization code, "fir_compiler_v3_1_config", caused the MATLAB error: Error calling function getPort. The return value from the function is a null pointer. Error occurred during "Rate and Type Error Checking". with regards ANIL
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sandeep.ism
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Registered: ‎05-22-2008
Don't know if u r still on this project but it seems that u r messing things up by adding the black box. Simply add fir compiler block with gateway blocks and the design will work.
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anee_anil
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Registered: ‎01-16-2008
thanks sandeep, i have tried that and that works nicely in simulation. but when i go for ISE or hardware i need to go for black box (as i thought). if u dont mind can u send one complete procedure of an low pass fir filter (from sysgen simulation to hardware implementation). please help me out. i have stuck up here since two months. Thanks and regards anil
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sandeep.ism
Contributor
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Registered: ‎05-22-2008

I am sorry but I do not understand why do u have to go for ISE or hardware? I mean u r using system generator  then u just need to go for hardware co simulation after a successful simulation.

Anyways here is what u needed.

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anee_anil
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Registered: ‎01-16-2008
Thanks sandeep It works good. thanks for your suggestion.

View solution in original post

28,738 Views
Registered: ‎04-19-2009

Hi,i am a student i tried following your work but i couldn't succeed,i am getting errors in simulation,can u please send me your filter simulation so that i can verify where i am going wrong.

 

thanx in advance

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8,701 Views
Registered: ‎04-19-2009

Hi all,any idea is required to design mismatch filter in System generator/simulink using barker codes as input for pulse compression.

please help

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