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Visitor
Visitor
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Registered: ‎07-10-2018

how to generate 4 MHz clock from 2 MHz clock in FPGA.

I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.

I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.

can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??

what are the other methods to do that??

 

Regards

Ankit

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Moderator
Moderator
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Registered: ‎08-16-2018

Re: how to generate 4 MHz clock from 2 MHz clock in FPGA.

Hi @ankitkes2 

 

Solution in the below post seems appropriate. 

https://forums.xilinx.com/t5/Synthesis/how-to-generate-4-MHz-clock-from-2-MHz-clock-in-FPGA/m-p/1074777#M34202


/ 7\7     Meher Krishna Patel, PhD
\ \        Senior Product Application Engineer, Xilinx
/ /        
\_\/\7   It is not so much that you are within the cosmos as that the cosmos is within you...
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