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Visitor
Visitor
11,297 Views
Registered: ‎06-02-2008

memory FIFO

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I have a problem when I want to implement the memory FIFO in System Generator. When I working with the FIFO incluided in SysGen displayed this error:

 

*** ERROR ***

Errors occurred during netlist generation.
Error using ==> sim
Error reported by S-function 'sysgen' in 'fifoSYS/FIFO':

Summary of errors from all sources:

 (NOTE: None of the errors were associated with a particular block;
  the block reporting this summary was chosen at random.)

--------------------------------------------------------------------------
Summary of Errors:
Error 0001: caught standard exception
     Block: Unspecified
--------------------------------------------------------------------------

Error 0001:

Reported by:
  Unspecified

Details:
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.f: ERROR:sim:160 - Could not find
requested IP (Fifo_Generator,2.3) for currently at
C:/matlab/toolbox/xilinx/sysgen/scripts/SgGenerateCores.pm line 590.

--------------------------------------------------------------------------.

So, I try to implement the FIFO using Core Generator, then, I import the model to System Generator with the block 'black blox'. The simulation in SysGen is OK, but when I want to implement is displayed the folowing error:

 

.....
Command Line: ngdbuild -p xc2vp30-7ff896 -nt timestamp -intstyle xflow
C:\matlab\work\Blackbox\coregen_import\example1\diseño\xflow/coregen_import_exam
ple1_cw.ngc coregen_import_example1_cw.ngd

Reading NGO file
'C:/matlab/work/Blackbox/coregen_import/example1/diseño/xflow/coregen_import_exa
mple1_cw.ngc' ...
Loading design module
"C:/matlab/work/Blackbox/coregen_import/example1/diseño/xflow/xlpersistentdff.ng
c"...
Executing edif2ngd -noa "fifo_generator_v2_1.edn" "fifo_generator_v2_1.ngo"
Release 8.1i - edif2ngd I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 8.1i edif2ngd I.24
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Writing module to "fifo_generator_v2_1.ngo"...
Loading design module
"C:\matlab\work\Blackbox\coregen_import\example1\diseño\xflow\fifo_generator_v2_
1.ngo"...

Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'coregen_import_example1_x0/black_box/BU2'
   with type 'fifo_generator_v2_1_fifo_generator_v2_1_ss_1' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol
   'fifo_generator_v2_1_fifo_generator_v2_1_ss_1' is not supported in target
   'virtex2p'.
WARNING:NgdBuild:443 - SFF primitive
   'default_clock_driver/xlclockdriver_1/clr_reg/reg_comp1/fdre_comp0' has
   unconnected output pin

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   1


One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "coregen_import_example1_cw.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...

 

 

Please help me, I need to implement a memory FIFO, using System Generator in a Virtex II Pro. I am using Xilinx 7.1, Matlab 7.1, System Generator 8.1

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Xilinx Employee
Xilinx Employee
11,779 Views
Registered: ‎08-02-2007
The problem is probably due to the fact that you have a newer version of System Generator than ISE. They should all agree on the version. ie. 8.1. AR 17966 discusses the dependencies between tool versions. If you are able to update to ISE 8.1 then do so. The error is probably because the IP is being looked for and it is not yet available because of ISE 7.1. Also check that you have the latest service pack for whichever version of ISE you will use.
RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com

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7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
11,780 Views
Registered: ‎08-02-2007
The problem is probably due to the fact that you have a newer version of System Generator than ISE. They should all agree on the version. ie. 8.1. AR 17966 discusses the dependencies between tool versions. If you are able to update to ISE 8.1 then do so. The error is probably because the IP is being looked for and it is not yet available because of ISE 7.1. Also check that you have the latest service pack for whichever version of ISE you will use.
RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com

View solution in original post

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Visitor
Visitor
11,258 Views
Registered: ‎06-02-2008

Thanks, I  updated the software and the problem was resolved. Now I have other problem when I want to compiled the model. the following error is displayed:

 

Begin generation
Checking model status
Checking simulation times
Performing compilation and generation

*** ERROR ***

Errors occurred during netlist generation.
Error using ==> sim
Error reported by S-function 'sysgen' in 'primera/Salida/Neurona/Adgd8':

Summary of errors from all sources:

 (NOTE: None of the errors were associated with a particular block;
  the block reporting this summary was chosen at random.)

--------------------------------------------------------------------------
Summary of Errors:
Error 0001: caught standard exception
     Block: Unspecified
--------------------------------------------------------------------------

Error 0001:

Reported by:
  Unspecified

Details:
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.f: ERROR:coreutil - Temporary directory
at C:/matlab/toolbox/xilinx/sysgen/scripts/SgGenerateCores.pm
line 590.

 

Please help me

 

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Adventurer
Adventurer
11,240 Views
Registered: ‎10-13-2007

For the following error :

Executing edif2ngd -noa "fifo_generator_v2_1.edn" "fifo_generator_v2_1.ngo"
Release 8.1i - edif2ngd I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 8.1i edif2ngd I.24
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Writing module to "fifo_generator_v2_1.ngo"...
Loading design module
"C:\matlab\work\Blackbox\coregen_import\example1\diseño\xflow\fifo_generator_v2_
1.ngo"...

Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'coregen_import_example1_x0/black_box/BU2'
   with type 'fifo_generator_v2_1_fifo_generator_v2_1_ss_1' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol
   'fifo_generator_v2_1_fifo_generator_v2_1_ss_1' is not supported in target
   'virtex2p'.
WARNING:NgdBuild:443 - SFF primitive
   'default_clock_driver/xlclockdriver_1/clr_reg/reg_comp1/fdre_comp0' has
   unconnected output pin

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   1
Make sure you have added all the core files (ngc, edn, +??) are added via the black box config.m file.

 

CTW

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Visitor
Visitor
7,543 Views
Registered: ‎04-10-2009

I have the same problem with jebricenoxs'. But the version of ISE i used is 8.1. I am using Matlab R2006a, System Generator 8.1.  I need help! Thank you!

 

this is the error i met:

*** ERROR ***

Errors occurred during netlist generation.
Error using ==> sim
Error reported by S-function 'sysgen' in

'NFDM_modulate/comwave/Register':

Summary of errors from all sources:

 (NOTE: None of the errors were associated with a particular

block;
  the block reporting this summary was chosen at random.)

-------------------------------------------------------------

-------------
Summary of Errors:
Error 0001: caught standard exception
     Block: Unspecified
-------------------------------------------------------------

-------------

Error 0001:

Reported by:
  Unspecified

Details:
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.f: ERROR:sim:160 - Could not find
requested IP (Fifo_Generator,2.3) for currently at
D:/MATLAB/R2006a/toolbox/xilinx/sysgen/scripts/SgGenerateCores

.pm
line 590.

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Highlighted
Visitor
Visitor
7,452 Views
Registered: ‎04-14-2009
You must provide more detailed version information on the versions you are using (i.e. ISE 8.1.? and System Generator 8.1.?).  Read the listings in the Xilinx Answer #17966 it list very specific versions of ISE 8.1.? and System Generator 8.1.? that are compatible with R2006a.
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Visitor
Visitor
7,446 Views
Registered: ‎04-10-2009
The version of ISE i am using is 8.1i and System Generator is 8.1.01. I am very sorry to trouble you because of my poor english.
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Highlighted
Observer
Observer
6,866 Views
Registered: ‎03-10-2009

this error i caused by wrong setting in system generator block, if it's set not to "clock enable"  then this happens.

The issue is definitely not sloved, cause I'm using veriosn 10.1

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