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Visitor
Visitor
4,292 Views
Registered: ‎02-08-2009

multirate clock options on the xilinx token(system generator)

i am designing a multi rate system on the system generator, i want to operate using a single clock and produce different rates using clock enables,, so i chose in the multi rate implementation options of the xilinx token "clock enables", when i took  the generated vhdl file on the xilinx ise and i formed a schematic symbol i found out that there is three clk inputs for the three different rates i used in my system, why is that?? i thought there will be one clk input and 3 clk enables inputs for my 3 rates???

 

 

can anybode suggest what might be the error??? thanks in advance

 

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Xilinx Employee
Xilinx Employee
4,286 Views
Registered: ‎08-16-2007

The machine generated RTL by SysGen can be hard to follow.  Make sure that you are looking a the top-level entity IO "<your_model_name>_cw" declaration and check if there are multiple clocks here.

 

-Chris 

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Newbie
Newbie
4,051 Views
Registered: ‎09-01-2009

I believe I am having the same issue. It would appear that my top level definition is creating both a second clock and an enable signal to do the second clock rate. The relevant part of the cw.vhd file (I think) is below.

 

test_x0: entity work.test

port map (

ce_1 => ce_1_sg_x0,

ce_8 => ce_8_sg_x0,

clk_1 => clk_1_sg_x0,

clk_8 => clk_8_sg_x0,

gateway_in => gateway_in_net,

gateway_in1 => gateway_in1_net,

gateway_out => gateway_out_net

);

 

Cheers,

Andy

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